參數(shù)資料
型號(hào)： ML60852
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： USB Device Controller
中文描述： USB設(shè)備控制器
文件頁(yè)數(shù)： 15/81頁(yè)
文件大?。?/td> 451K
代理商： ML60852
PEDL60852-01
1
Semiconductor
ML60852
15/81
(5) Data packet transmission and reception procedure during bulk transfer and interrupt transfer modes
The ML60852 is normally used on the peripheral device side. In this method of use, the ML60852 is connected on
one side to the host via the USB bus and is connected on the other side via a parallel interface to the local
microcontroller (local MCU) inside the peripheral device.
The transfer of data is the major function in all types of transfer modes other than the control transfer mode. When
carrying out transfer of data packets between the ML60852 and the host, the following packet communication is
carried out via the USB bus for the data transfer of each packet.
(a) Token packet transfer (IN token or OUT token) from the host to the ML60852.
(b) Data packet transfer in the desired direction (from the host to the device or from the device to the host).
(c) Transfer of handshake packet in a direction opposite to that of the data packet.
When packet transfer is completed normally, an ACK packet is returned in step (c) and the operation proceeds
to the next packet transfer.
The ML60852 requests the local MCU to transmit or receive a packet of data by asserting the
INTR
pin. The
interrupt cause will be “packet ready”. The transmit packet ready interrupt is one that requests that the packet
of data to be transmitted be written in the transmit FIFO, and the receive packet ready interrupt is one that
requests the local MCU to read out the data that has been received and stored in the receive FIFO.
The above procedures of transferring one packet of data are explained below for transmission and reception
separately.
1)
During transmission
The local MCU writes one packet of data that has to be transmitted in the transmit FIFO of the corresponding
EP in the ML60852, and sets the transmit packet ready bit of the corresponding EP status register of the
ML60852. When the host transmits the IN token packet to the ML60852 specifying the communication
method, etc., the ML60852 transmits to the host the data packet stored in the above transmit FIFO. When the
host receives one data packet normally, it returns the ACK packet to the ML60852. Consequently, the
ML60852 resets the transmit packet ready status, thereby completing the transfer of one data packet over the
USB bus. When the transmit packet ready status is reset, the ML60852 gives a request to the local MCU in
terms of a transmit packet ready interrupt thereby prompting the local MCU to write the next packet of data to
be transmitted.
During reception
The host sends to the ML60852 an OUT token followed by a data packet. The ML60852 stores the received
data packet in the receive FIFO of the corresponding EP. When it is confirmed that all the data packets have
been accumulated and that there is no error, the ML60852 returns an ACK packet to the host. At the same time,
the receive packet ready bit of the corresponding EP status register will also be set and a request is sent to the
local MCU in terms of an interrupt. Upon receiving this interrupt, the local MCU reads out the received data
from the ML60852 and resets the receive packet ready bit.
2)
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相關(guān)代理商/技術(shù)參數(shù)
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