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參數(shù)資料
| 型號： | ML53101 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 10/100 Mbps 8-Port Ethernet/Fast Ethernet Media Access Controller(10/100Mbps的8口以太網(wǎng)媒介存儲控制器) |
| 中文描述： | 10/100 Mbps的8端口以太網(wǎng)/快速以太網(wǎng)媒體訪問控制器（10/100的8口以太網(wǎng)媒介存儲控制器） |
| 文件頁數(shù)： | 8/21頁 |
| 文件大?。?/td> | 188K |
| 代理商： | ML53101 |
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ML53101 8-Port Fast Ethernet Controller
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Oki Semiconductor
Figure 2. FIFO Structure and Data Flow
Each MAC has a pair of working FlFOs for TX and RX. The RX FIFO is 64 bits wide. The TX FIFO is byte
wide internally, with a 64-bit by 8-word gateway FIFO for high speed data transfers from the bus. Pro-
grammable threshold block size is 4 and 8 data words of 64-bit width.
External signals provide a means to monitor the FIFO status through the 32-bit PCI bus. There is a transmit
FIFO ready signal using the programmable threshold block size. There is a receive FIFO data present sig-
nal using the programmable threshold block size (or the EOF signal). Incomplete words are indicated with
the Byte Valid signal.
The FIFO host transmit and receive data transfer process is based on a 64-bit bidirectional high-speed bus
interface. Each MAC has a 3-bit address, a Device Chip Select, and TX/ RX data ready indicators. All data
is transferred under control of a host device using the 3-bit address.
The functional timing diagrams at the end of this document illustrate the data flow between the host
device and one of the eight MAC FlFOs.
FCLK
FCLK
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
32
32
32
32
32
32
32
32
FCLK
MTCLK
64
64
64
64
64
64
64
8
8
8
8
8
8
8
8
64
FCLK
MRCLK
MTCLK
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
MAC
MAC
MAC
MAC
MAC
MAC
MAC
MAC
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