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參數(shù)資料
| 型號(hào)： | ML53101 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 10/100 Mbps 8-Port Ethernet/Fast Ethernet Media Access Controller(10/100Mbps的8口以太網(wǎng)媒介存儲(chǔ)控制器) |
| 中文描述： | 10/100 Mbps的8端口以太網(wǎng)/快速以太網(wǎng)媒體訪問控制器（10/100的8口以太網(wǎng)媒介存儲(chǔ)控制器） |
| 文件頁數(shù)： | 2/21頁 |
| 文件大?。?/td> | 188K |
| 代理商： | ML53101 |
I
ML53101 8-Port Fast Ethernet Controller
I
––––––––––––––––––––––––––––––––––––––––––––––––––––––––
2
Oki Semiconductor
FEATURES
8-port full-duplex 10/ 100 Mbps MAC in one
single device.
8 independent MACs and MIIs.
Ports independently selectable for
10/ 100 Mbps.
Full CMIB Statistics Information Base for
remote monitoring (RMON) support.
Shared 64-bit, 66-MHz FIFO Interface for TX
and RX data transfer.
FIFO bus bandwidth exceeds 4 Gbps.
Shared 32-bit PCI interface for control, status,
and statistics information exchange.
RX Frame Status can be appended at the end
of a frame as an additional 64-bit data word
on the FIFO Interface.
Independent dual-port RX and TX FlFOs for
each MAC.
Programmable FIFO burst size of
32/ 64 bytes.
Transmit FIFO ready signal per channel
using the TX FIFO burst size as threshold.
Auto retransmit of transmit data upon
tranmist collision condition.
Receive FIFO ready signal per channel using
the RX FIFO burst size as threshold or end of
frame (EOF).
Receive data ready hold-off enable for
minimum receive packet size (runt removal).
Byte Valid signal for each byte in the 64-bit
data word for TX and RX.
Full-duplex flow control (conformant to the
IEEE 802.3x Ethernet standards proposal).
Pin-initiated Pause Frame with
preprogrammed Pause Time.
Half-duplex flow control using Carrier Sense
(deferral instead of collision).
Pin-controlled carrier (jam) assertion
independently per port.
7-wire interface, selectable for connecting to a
low-cost l0-Mbps physical layer or for using
an MII interface to connect to a 10- or l00-
Mbps physical layer using auto-negotiation.
HUGE Packet Enable on a per-packet basis,
always, or never.
CRC Recalculation Enable on a per-packet
basis, always, or never.
Supports 802.3i, 802.3u, 802.3x, 802.3y and
802.3 IEEE standards as well as 8802-3 ANSI
Ethernet standards.
Technology used is CMOS 0.35
μ
m, 3.3 V.
Package is a 352-pin BGA.
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