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參數(shù)資料
| 型號(hào)： | ML53101 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 10/100 Mbps 8-Port Ethernet/Fast Ethernet Media Access Controller(10/100Mbps的8口以太網(wǎng)媒介存儲(chǔ)控制器) |
| 中文描述： | 10/100 Mbps的8端口以太網(wǎng)/快速以太網(wǎng)媒體訪問控制器（10/100的8口以太網(wǎng)媒介存儲(chǔ)控制器） |
| 文件頁數(shù)： | 3/21頁 |
| 文件大?。?/td> | 188K |
| 代理商： | ML53101 |
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I
ML53101 8-Port Fast Ethernet Controller
I
3
Oki Semiconductor
SIGNAL DESCRIPTIONS
The signal descriptions for the various MAC interfaces are summarized in the following sections. Active-
LOW signals are denoted with an asterisk (*) after the signal name (for example, CS*).
FIFO Bus Interface
Table 1 FIFO Bus Interface Signals
Signal Name
Description
I/O
RXDRDY[7:0]
Receive Data Ready.
available in the receive FIFO on the indicated port.
The MAC8110 asserts these signals to indicate that a threshold number of bytes are
TTL Output
TXDRDY[7:0]
Transmit Data Ready.
are available in the transmit FIFO for new data on the indicated port.
The MAC8110 asserts these signals to indicate that a threshold number of locations
TTL Output
ADDR[2:0]
Port Address.
address on these inputs.
The host selects a FIFO port for access on the FIFO bus by placing the binary encoded port
TTL Input
CS*
Chip Select.
This pin is asserted LOW when the device is selected for data transfer.
TTL Input
BVAL[7:0]
Byte Valid.
transfer using these signals.
The FIFO data originator indicates the validity of respective data bytes within the 64-bit FIFO
TTL l/O
R/W*
FIFO Read/FlFO Write.
When the pin is HIGH a read is indicated; when LOW, the pin indicates a write operation.
The host asserts this signal to indicate the data direction for a FIFO bus transfer.
TTL Input
TREN*
Transfer Enable.
Enables FIFO transfers.
TTL Input
SOF
Start of Frame.
written or read is the first word in the frame.
The FIFO data originator asserts this signal HIGH to indicate that the current word being
TTL l/O
EOF
End of Frame.
written or read is the last word in the frame.
The FIFO data originator asserts this signal HIGH to indicate that the current word being
TTL l/O
DATA[63:0]
FIFO Data Bus.
Carries data for the FIFO interface.
TTL l/O
RESET
Reset.
When the host asserts this signal HIGH, a general reset of the entire chip occurs.
TTL Input
FCLK
FIFO Bus Clock.
The host will provide the FIFO bus clock; maximum clock rate equals 66 MHz
TTL Input
CRC_EN
CRC Enable.
CRC value.
When asserted, the CRC_EN signal indicates that the MAC8110 must recalculate the frame’s
TTL Input
HUGE_EN
Huge Enable.
Enables the passage of oversized frames through the MAC8110.
TTL Input
PAD_EN
Pad Enable.
through it.
When asserted, PAD_EN indicates that the MAC8110 must pad undersized frames that pass
TTL Input
FCTL_Start
Flow Control Start.
Initiates the start of a flow control sequence in both Full-Duplex and Half-Duplex modes. TTL Input
FCTL_End
Flow Control End.
Terminates a flow control sequence in Half-Duplex Mode.
TTL Input
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