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參數(shù)資料
| 型號(hào)： | MK30N512VMB100 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA81 |
| 封裝： | 8 X 8 MM, MAPBGA-81 |
| 文件頁數(shù)： | 30/62頁 |
| 文件大?。?/td> | 1728K |
| 代理商： | MK30N512VMB100 |
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FIGURE TBD
Figure 12. Typical ENOB vs. Averaging for 16-bit differential and 16-bit single-ended
modes
6.6.1.3 16-bit ADC with PGA operating conditions
Table 25. 16-bit ADC with PGA operating conditions
Symbol
Description
Conditions
Min.
Max.
Unit
Notes
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
VREFPGA PGA ref voltage
VREFOUT VREFOUT VREFOUT
V
VADIN
Input voltage
VSSA
—
VDDA
V
VCM
Input Common
Mode range
VSSA
—
VDDA
V
RPGAD
Differntial input
impedance
Gain = 1, 2, 4, 8
Gain = 16, 32
Gain = 64
—
128
64
32
—
kΩ
IN+ to IN-4
RAS
Analog source
resistance
—
100
—
Ω
TS
ADC sampling
time
1.25
—
s
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. ADC must be configured to use the internal voltage reference (VREFOUT)
3. PGA reference connected to the VREFOUT pin. If the user wishes to drive VREFOUT with a voltage other than the output
of the VREF module, the VREF module must be disabled.
4. For single ended configurations the input impedence of the driven input is 1/2.
5. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25s
time should be allowed for Fin=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
8 MHz ADC clock.
6.6.1.4 16-bit ADC with PGA characteristics
Table 26. 16-bit ADC with PGA characteristics
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
IDDA_PGA
Supply current
—
590
TBD
μA
IDC_PGA
Input DC current
A
IILKG
Input Leakage
current
PGA disabled
—
TBD
μA
Table continues on the next page...
Peripheral operating requirements and behaviors
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
36
Preliminary
Freescale Semiconductor, Inc.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MK30N512VMC100 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz |
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| MK30R1F | 制造商:Ohmite Mfg Co 功能描述: |
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