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| 型號： | MEA224AG |
| 廠商： | CONEXANT SYSTEMS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PBGA352 |
| 封裝： | 35 X 35 MM, 2.33 MM HEIGHT, PLASTIC, MS-034, BGA-352 |
| 文件頁數(shù)： | 8/29頁 |
| 文件大?。?/td> | 519K |
| 代理商： | MEA224AG |
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PRELI
MI
NARY
D
A
TA
S
H
EET
XpressFlow-2001 Series –
EA-224
Ethernet Switch Chip-set
4-Port 10/100M Ethernet Access Controller
1997 Zarlink Semiconductor Inc.
Page: 15
Rev. 4.0 –December, 1997
4.3 XpressFlow Bus Operation
Zarlink’s optimized XpressFlow Bus architec-
ture
Provides up to 1.6G bps switching bandwidth
-33
1.07G bps
-40
1.28G bps
-50
1.60G bps
Full multi bus master structure
Allows Access Controllers to communicate
with XpressFlow Engine and other Access
Controllers via a message passing protocol
Two level bus request priorities
High priority for Data Messages
for forwarding an Ethernet frame from
receiving port to transmission port
Low priority for Command Messages
for passing control information between
devices
4.3.1 Pin Description
Symbol
Type
Name & Functions
S_D[31:0]
CMOS
I/O-TS
Data Bus Bit [31:0] – a 32-bit synchronous data bus.
Note:
During the system RESET period, Data Bit [31:27] are used
as Processor Interface Configuration bit [0:3]
S_MSGEN#
CMOS
I/O-TS
Message Envelope – encompasses the entire period of a message
transfer. Targets use the leading edge of this signal to detect the be-
ginning of a message transfer, and to decode the message header for
the intended target(s).
S_EOF#
CMOS
I/O-TS
End of Frame – only used by frame data transfer messages to identify
the end of frame condition. This signal is synchronous with the Rx
Frame Status word appended to the end of the message.
S_IRDY
CMOS
I/O-TS
Initiator Ready – a normal true signal. When negated, it indicates the
initiator had asserted wait state(s) in between command words. Target
should use this signal as enable signal for latching the data from the
bus.
S_TABT#
CMOS
I/O-OD
Target Abort – when asserted, the target had aborted the reception of
current message on the bus.
S_HPREQ#
CMOS
I/O-OD
High Priority Request – indicates one or more Bus Requester is re-
questing for high priority message transfer.
S_REQ#
CMOS
Output
Bus Request – Bus Request signal from Access Controller to Bus Ac-
cess Arbitrator in XpressFlow Engine
S_GNT#
CMOS
Input
Bus Grant – Bus Grant signal from Bus Arbitrator to Bus Requester
S_OVLD#
CMOS
Input
Bus Over-load – when asserted, all data forwarding bus bandwidth has
been allocated. Cannot support additional load for data forwarding traf-
fic.
S_CLK
CMOS
Input
XpressFlow Bus Clock – up to 50MHz system clock
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