參數(shù)資料
型號(hào)： MEA224AG
廠(chǎng)商： CONEXANT SYSTEMS
元件分類(lèi)： 微控制器/微處理器
英文描述： 4 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PBGA352
封裝： 35 X 35 MM, 2.33 MM HEIGHT, PLASTIC, MS-034, BGA-352
文件頁(yè)數(shù)： 11/29頁(yè)
文件大?。?/td> 519K
代理商： MEA224AG
PRELI
MI
NARY
D
A
TA
S
H
EET
XpressFlow-2001 Series –
EA-224
Ethernet Switch Chip-set
4-Port 10/100M Ethernet Access Controller
1997 Zarlink Semiconductor Inc.
Page: 18
Rev. 4.0 –December, 1997
4.4 MII Interface
Fully compliant with IEEE 802.3u Media Inde-
pendent Interface for connecting with external
10/100M Ethernet Physical Layer Transceiver
Supports both 10Mbps 10BaseT interface and
100Mbps 100BaseTx interface
Supports both half and full duplex operation
Shared Station Management interface (one for
all MII channels with in the Access Controller)
All ports can also support 10Mbps Serial In-
terface
If 10Mbps Serial Interface is used, the MII
port pin assignment are re-mapped for
10Mbps Serial Interface.
4.4.1 Pin Description
Symbol
Type
Name & Functions
M_MDC
CMOS
Output
MII Management Data Clock – (common for all MII Ports) used to syn-
chronize the MII data stream (MDIO) for transferring between the Ac-
cess Controller and the MII Tranceivers.
M_MDIO
TTL
IO-TS
(5VT)
MII Management Data I/O – (common for all MII Ports) a serial man-
agement data stream synchronous with MDC.
Mm_RXD[3:0] TTL In
(5VT)
Receive Data [3:0] – (one set for each MII Port) a four-bit transmit data
nibble. Bit 0 is the least significant bit, and bit 3 is the most significant
bit.
Mm_RXDV
TTL In
(5VT)
Receive Data Valid – (one for each MII Port) instructs the MAC to be-
gin moving data nibbles from the receive data lines.
Mm_RXC
TTL In
(5VT)
Receive Clock – (one for each MII Port) a 25MHz clock input with 35%
to 65% duty cycles.
Mm_RXER
TTL In
(5VT)
Receive Error – (one for each MII Port)
Mm_TXER
CMOS
Output
Transmit Error – (one for each MII Port)
Mm_TXC
TTL In
(5VT)
Transmit Clock – (one for each MII Port) a continuous clock input with
35% to 65% duty cycles.
Mm_TXEN
CMOS
Output
Transmit Enable – (one for each MII Port) instructs the transceiver to
begin moving data nibbles on the transmit data lines.
Mm_TXD[3:0] CMOS
Output
Transmit Data [3:0] – (one set for each MII Port) a four-bit transmit
data nibble. Bit 0 is the least significant bit, and bit 3 is the most signifi-
cant bit.
Mm_COL
TTL In
(5VT)
Collision Detected – (one for each MII Port)
Mm_CRS
TTL In
(5VT)
Carrier Sense – (one for each MII Port)
Mm_LNK
?
TTL In
(5VT)
Link Status – (one for each MII Port)
The polarity of this signal is programmable via Port Configuration Reg-
ister
Note:
“m” is the port number [3:0].
?
These signals have programmable output polarity.
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