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| 型號： | MEA224AG |
| 廠商： | CONEXANT SYSTEMS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PBGA352 |
| 封裝： | 35 X 35 MM, 2.33 MM HEIGHT, PLASTIC, MS-034, BGA-352 |
| 文件頁數(shù)： | 26/29頁 |
| 文件大小： | 519K |
| 代理商： | MEA224AG |
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PRELI
MI
NARY
D
A
TA
S
H
EET
XpressFlow-2001 Series –
EA-224
Ethernet Switch Chip-set
4-Port 10/100M Ethernet Access Controller
1997 Zarlink Semiconductor Inc.
Page: 5
Rev. 4.0 –December, 1997
Pin No(s).
Symbol
Type
Max
IOL / IOH Name & Functions
Control Buffer Memory Interface
M4,N2,L3,M1,M2,L1,K3,
L2,K4,K1,J3,K2,J1,J2,
H3,H1,H2,G3,G1,G2,F1,
F3,F2,E1,E3,E2,D1,D3,
D2,C1,C2,B1
L_D[31:0]
TTL I/O-TS
@
8mA
Local Memory Bus – Data Bit [31:0]
A6,B6,C8,A7,D8,D7,C9,
A8,B8,A9,C10,B9,D10,
A10,C11,B10,A11
L_A[18:2]
CMOS Output
8mA
Local Memory Bus – Address Bit [17:2]
C7
L_A[19] /
L_OE[3]#
CMOS Output
8mA
Local Memory Bus – Address Bit [19] or
Memory Read Chip Select [3]
D5,A5,A3
L_OE[2:0]#
CMOS Output
2mA
Local Memory Read Chip Select [2:0]
D7,E4,B5,C4
L_WE[3:0]#
CMOS Output
2mA
Local Memory Write Chip Select [3:0]
C6,B4,A4,C5
L_BWE[3:0]#
CMOS Output
8mA
Local Memory Byte Write Enable, Byte
[3:0]
B3
L_ADSC#
CMOS Output
8mA
Local Memory Controller Address Status
G4
L_CLK
CMOS Output
8mA
Local Memory Clock input
Fast Ethernet Access Port [3:0]
T24M_MDC
CMOS Output
4mA
MII Management Data Clock – (common
for all MII Ports – Port [1:0])
R26
M_MDIO
TTL IO-TS
(5VT)
4mA
MII Management Data I/O – (common for
all MII Ports – Port [1:0]))
AB2,U25,AE26,AF5
M[3:0]_RXD[3] TTL In (5VT)
@
Port [3:0] – MII Receive Data Bit [3]
AB1,V24,AD25,AE6
M[3:0]_RXD[2] TTL In (5VT)
@
Port [3:0] -- Receive Data Bit [2]
AA3,U26,AD26,AD6
M[3:0]_RXD[1] TTL In (5VT)
@
Port [3:0] -- Receive Data Bit [1]
AC2,T25
M[3:2]_RXD[0] TTL In (5VT)
@
Port [3:0] -- Receive Data Bit [0]
AC25,AF6
M[1:0]_RXD[0] TTL In (5VT)
Y3,V26,AF24,AD5
M[3:0]_RXDV TTL In (5VT)
@
Port [3:0] -- Receive Data Valid
AC1,U24
M[3:2]_RXC
TTL In (5VT)
@
Port [3:0] -- Receive Clock
AC24,AE7
M[1:0]_RXC
TTL In (5VT)
AA1,V25,AD23,AE5
M[3:0]_RXER
Port [3:0] -- Receive Error
AA2,W24,AE24,AF4
M[3:0]_TXER
CMOS Output
4mA
Port [3:0] -- Transmit Error
W2,AA25,AE22,AD1
M[3:0]_TXC
TTL In (5VT)
Port [3:0] -- Transmit Clock
W1,AA24,AF22,AF2
M[3:0]_TXEN
CMOS Output
4mA
Port [3:0] -- Transmit Enable
V3,AA26,AD21,AE3
M[3:0]_TXD[3] CMOS Output
4mA
Port [3:0] -- Transmit Data Bit [3]
Y2,Y26,AE23,AF3
M[3:0]_TXD[2] CMOS Output
4mA
Port [3:0] -- Transmit Data Bit [2]
W3,W26,AD22,AD4
M[3:0]_TXD[1] CMOS Output
4mA
Port [3:0] -- Transmit Data Bit [1]
Y1,W25,AF23,AE4
M[3:0]_TXD[0] CMOS Output
4mA
Port [3:0] -- Transmit Data Bit [0]
V1,AB26
M[3:2]_COL
TTL In (5VT)
@
Port [3:0] -- Collision Detected
AD20,AC3
M[1:0]_COL
TTL In (5VT)
U3,AB24
M[3:2]_CRS
TTL In (5VT)
@
Port [3:0] -- Carrier Sense
AF21,AD2
M[1:0]_CRS
TTL In (5VT)
V2,AB25
M[3:2]_LNK
? TTL In (5VT) @
Port [3:0] -- Link Status
AE21,AB3
M[1:0]_LNK
? TTL In (5VT)
Test Facility
A25
T_MODE
CMOS I/O-TS
@
2mA
Test Pin – Set Test Mode upon Reset,
and provides test status output during
test mode
N1,M3,P2,P1,N3,R2,P3,
R1,T2,R3,T1,R4,U2,T3,
U1,U4
T_D[15:10]
A CMOS Output
4mA
Test Pins – Reserved for internal use
only
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