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2009 Microchip Technology Inc.
DS41399A-page 65
MCV18E
9.0
SPECIAL FEATURES OF THE
CPU
The MCV18E device has a host of features intended to
maximize system reliability, minimize cost through
elimination of external components, provide power-
saving operating modes and offer code protection.
These are:
OSC Selection
Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
Interrupts
Watchdog Timer (WDT)
Sleep
Code protection
ID locations
In-Circuit Serial Programming (ICSP)
The MCV18E device has a Watchdog Timer, which can
be shut off only through Configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
the chip in Reset until the crystal oscillator is stable.
The other is the Power-up Timer (PWRT), which pro-
vides a fixed delay on power-up only and is designed to
keep the part in Reset while the power supply stabi-
lizes. With these two timers on-chip, most applications
need no external Reset circuitry.
Sleep mode is designed to offer a very low-current
Power-Down mode. The user can wake-up from Sleep
through external Reset, Watchdog Timer Wake-up, or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost, while the
LP crystal option saves power. A set of Configuration
bits are used to select various options.
9.1
Configuration Bits
The Configuration bits can be programmed (read as
‘0’) or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped in
program memory location 2007h.
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
special configuration memory space (2000h-3FFFh),
which can be accessed only during programming.