參數(shù)資料
型號(hào): MCIMX281AVM4B
廠商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 微控制器/微處理器
英文描述: 32-BIT, 454 MHz, RISC PROCESSOR, PBGA289
封裝: 14 X 14 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, MAPBGA-289
文件頁(yè)數(shù): 40/72頁(yè)
文件大?。?/td> 915K
代理商: MCIMX281AVM4B
i.MX28 Applications Processors Data Sheet for Automotive Products, Rev. 1
Freescale Semiconductor
45
3.5.9
Inter IC (I2C) Timing
The I2C module is designed to support up to 400-Kbps I2C connection compliant with I2C bus protocol.
The following section describes I2C SDA and SCL signal timings.
Figure 25 shows the timing of the I2C module. Table 50 describes the I2C module timing parameters
(IC1–IC11) shown in the figure.
Figure 25. I2C Module Timing Diagram
Table 50. I2C Module Timing Parameters: 1.8 V
3.6 V
ID
Parameter
Standard Mode
Fast Mode
Unit
Min.
Max.
Min.
Max.
IC1
I2C_SCL cycle time
10
2.5
μs
IC2
Hold time (repeated) START condition
4.0
0.6
μs
IC3
Set-up time for STOP condition
4.0
0.6
μs
IC4
Data hold time
01
1 A device must internally provide a hold time of at least 300 ns for the I2C_SDA signal in order to bridge the undefined region
of the falling edge of I2C_SCL.
3.452
2 The maximum IC4 has to be met only if the device does not stretch the LOW period (ID no IC5) of the I2C_SCL signal.
μs
IC5
HIGH Period of I2C_SCL clock
4.0
0.6
μs
IC6
LOW Period of the I2C_SCL clock
4.7
1.3
μs
IC7
Set-up time for a repeated START condition
4.7
0.6
μs
IC8
Data set-up time
250
1003
3 A fast-mode I2C bus device can be used in a standard-mode I2C bus system, but the requirement of Set-up time (ID No IC7)
of 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the I2C_SCL signal.
If such a device does stretch the LOW period of the I2C_SCL signal, it must output the next data bit to the I2C_SDA line
max_rise_time (ID No IC9) + data_setup_time (ID No IC7) = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus
specification) before the I2C_SCL line is released.
—ns
IC9
Bus free time between a STOP and START condition
4.7
1.3
μs
IC10
Rise time of both I2C_SDA and I2C_SCL signals
1000
20+0.1Cb
4
4 C
b = total capacitance of one bus line in pF.
300
ns
IC11
Fall time of both I2C_SDA and I2C_SCL signals
300
20+0.1Cb
300
ns
IC12
Capacitive load for each bus line (Cb)
400
400
pF
IC10
IC11
IC9
IC2
IC8
IC4
IC7
IC3
IC6
IC10
IC5
IC11
START
STOP
START
I2C_SDA
I2C_SCL
IC1
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