參數(shù)資料
型號: MCIMX258CJM4
廠商: Freescale Semiconductor
文件頁數(shù): 98/153頁
文件大?。?/td> 0K
描述: MPU IMX25 IND 400-MAPBGA
特色產(chǎn)品: MCIMX25 Applications Processors
標(biāo)準(zhǔn)包裝: 90
系列: i.MX25
核心處理器: ARM9
芯體尺寸: 32-位
速度: 400MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),I²C,MMC,智能卡,SPI,SSI,UART/USART,USB OTG
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 128
程序存儲器類型: 外部程序存儲器
RAM 容量: 144K x 8
電壓 - 電源 (Vcc/Vdd): 1.15 V ~ 1.52 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 3x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 400-LFBGA
包裝: 托盤
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor
49
Figure 17 shows timing for device-terminated UDMA in-transfer.
Figure 17. Timing for Device-Terminated UDMA Transfer
Timing parameters for UDMA in-burst are listed in Table 39.
Table 39. Timing Parameters for UDMA In-Burst
ATA
Parameter
Spec.
Parameter
Value
Required Conditions
tack
tack(min.) = (time_ack
× T) – (tskew1 + tskew2)
time_ack
tenv
tenv(min.) = (time_env
× T) – (tskew1 + tskew2)
tenv(max.) = (time_env
× T) + (tskew1 + tskew2)
time_env
tds
tds1
tds – (tskew3) – ti_ds > 0
tskew3, ti_ds, ti_dh
should be low enough
tdh
tdh1
tdh – (tskew3) –ti_dh > 0
tcyc
tc1
(tcyc – tskew) > T
T big enough
trp
trp(min.) = time_rp
× T – (tskew1 + tskew2 + tskew6)
time_rp
—tx11
1 There is a special timing requirement in the ATA host that requires the internal DIOW to go only high three clocks after the last
active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint.
Make ton and toff big enough to avoid bus contention.
(time_rp
× T) – (tco + tsu + 3T + 2 × tbuf + 2 × tcable2) > trfs (drive)
time_rp
tmli
tmli1
tmli1(min.) = (time_mlix + 0.4)
× T
time_mlix
tzah
tzah(min.) = (time_zah + 0.4)
× T
time_zah
tdzfs
tdzfs = (time_dzfs
× T) – (tskew1 + tskew2)
time_dzfs
tcvh
tcvh = (time_cvh
× T) – (tskew1 + tskew2)
time_cvh
—ton
toff
ton = time_on
× T – tskew1
toff = time_off
× T – tskew1
DMARQ
ADDR
DIOR
DIOW
IORDY
DATA READ
DMACK
tds
tdh
tc1
DATA WRITE
buffer_en
tack
tss1
tzah
ton tdzfs tcvh
toff
tzah
tmli
tli5
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