參數(shù)資料
型號: MCIMX258CJM4
廠商: Freescale Semiconductor
文件頁數(shù): 136/153頁
文件大?。?/td> 0K
描述: MPU IMX25 IND 400-MAPBGA
特色產(chǎn)品: MCIMX25 Applications Processors
標準包裝: 90
系列: i.MX25
核心處理器: ARM9
芯體尺寸: 32-位
速度: 400MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),I²C,MMC,智能卡,SPI,SSI,UART/USART,USB OTG
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 128
程序存儲器類型: 外部程序存儲器
RAM 容量: 144K x 8
電壓 - 電源 (Vcc/Vdd): 1.15 V ~ 1.52 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 3x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 400-LFBGA
包裝: 托盤
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor
83
3.7.8
Enhanced Secured Digital Host Controller (eSDHCv2) Timing
Figure 54 shows eSDHCv2 timing, and Table 61 describes the timing parameters (SD1–SD8) used in the
figure. The following definitions apply to values and signals described in Table 61:
LS: low-speed mode. Low-speed card can tolerate clocks up to 400 kHz
FS: full-speed mode. Full-speed MMC card’s clock can reach 20 MHz; full speed SD/SDIO card
clock can reach 25 MHz
HS: high-speed mode. High-speed MMC card’s clock can reach 52 MHz; SD/SDIO card clock can
reach 50 MHz
86
SCKT rising edge to data out valid
18.0
13.0
x ck
i ck
ns
87
SCKT rising edge to data out high
impedance6
——
21.0
16.0
x ck
i ck
ns
88
SCKT rising edge to transmitter #0 drive
enable negation6
——
14.0
9.0
x ck
i ck
ns
89
FST input (bl, wr) setup time before SCKT
falling edge5
——
2.0
18.0
x ck
i ck
ns
90
FST input (wl) setup time before SCKT falling
edge
——
2.0
18.0
x ck
i ck
ns
91
FST input hold time after SCKT falling edge
4.0
5.0
x ck
i ck
ns
92
FST input (wl) to data out enable from high
impedance
21.0
ns
93
FST input (wl) to transmitter #0 drive enable
assertion
14.0
ns
94
Flag output valid after SCKT rising edge
14.0
9.0
x ck
i ck
ns
95
HCKR/HCKT clock cycle
2 x TC
15
ns
96
HCKT input rising edge to SCKT output
18.0
ns
97
HCKR input rising edge to SCKR output
18.0
ns
1 V
CORE_VDD = 1.00 ± 0.10 V; TJ = –40 °C to 125 °C, CL = 50 pF
2 In the “Characteristics” column, bl = bit length, wl = word length, wr = word length relative
3 In the “Expression” column, T
C = 7.5 ns.
4 For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
5 The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync
signal waveform, but spreads starting from one serial clock before the first bit clock (same as the bit length frame sync signal),
until the second-to-last bit-clock of the first word in the frame.
6 Periodically sampled and not 100% tested.
Table 60. ESAI General Timing Requirements (continued)
No.
Characteristics1 2
Symbol
Expression3
Min.
Max.
Condition
Unit
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