參數(shù)資料
型號： MCHC11F1CFNE5
廠商： Freescale Semiconductor
文件頁數(shù)： 29/158頁
文件大小： 0K
描述： MCU 8BIT 1KRAM 512EE 68-PLCC
標(biāo)準(zhǔn)包裝： 18
系列： HC11
核心處理器： HC11
芯體尺寸： 8-位
速度： 5MHz
連通性： SCI，SPI
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 30
程序存儲器類型： ROMless
EEPROM 大小： 512 x 8
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x8b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 68-LCC（J 形引線）
包裝： 管件
TIMING SYSTEM
MC68HC11F1
9-18
TECHNICAL DATA
9.6.3 Pulse Accumulator Status and Interrupt Bits
The pulse accumulator control bits, PAOVI, PAII, PAOVF, and PAIF are located within
timer registers TMSK2 and TFLG2.
PAOVI and PAOVF — Pulse Accumulator Interrupt Enable and Overflow Flag
The PAOVF status bit is set each time the pulse accumulator count rolls over from $FF
to $00. To clear this status bit, write a one in the corresponding data bit position (bit 5)
of the TFLG2 register. The PAOVI control bit allows configuring the pulse accumulator
overflow for polled or interrupt-driven operation and does not affect the state of
PAOVF. When PAOVI is zero, pulse accumulator overflow interrupts are inhibited, and
the system operates in a polled mode, which requires that PAOVF be polled by user
software to determine when an overflow has occurred. When the PAOVI control bit is
set, a hardware interrupt request is generated each time PAOVF is set. Before leaving
the interrupt service routine, software must clear PAOVF by writing to the TFLG2 reg-
ister.
PAII and PAIF — Pulse Accumulator Input Edge Interrupt Enable and Flag
The PAIF status bit is automatically set each time a selected edge is detected at the
PA7/PAI/OC1 pin. To clear this status bit, write to the TFLG2 register with a one in the
corresponding data bit position (bit 4). The PAII control bit allows configuring the pulse
accumulator input edge detect for polled or interrupt-driven operation but does not af-
fect setting or clearing the PAIF bit. When PAII is zero, pulse accumulator input inter-
rupts are inhibited, and the system operates in a polled mode. In this mode, the PAIF
bit must be polled by user software to determine when an edge has occurred. When
the PAII control bit is set, a hardware interrupt request is generated each time PAIF is
set. Before leaving the interrupt service routine, software must clear PAIF by writing to
the TFLG2 register.
TMSK2 — Timer Interrupt Mask 2 Register
$1024
Bit 7
654321
Bit 0
TOI
RTII
PAOVI
PAII
—
PR1
PR0
RESET:
0000000
0
TFLG2 — Timer Interrupt Flag 2 Register
$1025
Bit 7
654321
Bit 0
TOF
RTIF
PAOVF
PAIF
—
RESET:
0000000
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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