參數(shù)資料
型號: MCHC11F1CFNE5
廠商: Freescale Semiconductor
文件頁數(shù): 154/158頁
文件大?。?/td> 0K
描述: MCU 8BIT 1KRAM 512EE 68-PLCC
標(biāo)準(zhǔn)包裝: 18
系列: HC11
核心處理器: HC11
芯體尺寸: 8-位
速度: 5MHz
連通性: SCI,SPI
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 30
程序存儲器類型: ROMless
EEPROM 大?。?/td> 512 x 8
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 68-LCC(J 形引線)
包裝: 管件
SERIAL COMMUNICATIONS INTERFACE
TECHNICAL DATA
7-9
RCKB — SCI Baud Rate Clock Check (Test)
SCR[2:0] — SCI Baud Rate Selects
Selects receiver and transmitter bit rate based on output from baud rate prescaler
stage. Refer to the SCI baud rate generator block diagram.
The prescaler bits, SCP[2:0], determine the highest baud rate, and the SCR[2:0] bits
select an additional binary submultiple (
≥1, ≥2, ≥4, through ≥128) of this highest baud
rate. The result of these two dividers in series is the 16X receiver baud rate clock. The
SCR[2:0] bits are not affected by reset and can be changed at any time, although they
should not be changed when any SCI transfer is in progress.
Figure 7-3 and Figure 7-4 illustrate the SCI baud rate timing chain. The prescaler se-
lect bits determine the highest baud rate. The rate select bits determine additional di-
vide by two stages to arrive at the receiver timing (RT) clock rate. The baud rate clock
is the result of dividing the RT clock by 16.
Table 7-2 Baud Rate Selection
Divide
Prescaler
Highest Baud Rate
(Prescaler Output from Previous Table)
SCR[2:0]
By
4800
19200
76800
312500
0 0 0
1
4800
19200
76800
312500
0 0 1
2
2400
9600
38400
0 1 0
4
1200
4800
19200
78125
0 1 1
8
600
2400
9600
39063
1 0 0
16
300
1200
4800
19531
1 0 1
32
150
600
2400
9766
1 1 0
64
75
300
1200
4883
1 1 1
128
150
600
2441
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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