參數(shù)資料
型號(hào): MCF52277CVM166
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 166.67 MHz, RISC PROCESSOR, PBGA196
封裝: 15 X 15 MM, PLASTIC, ROHS COMPLIANT, MAPBGA-196
文件頁(yè)數(shù): 32/42頁(yè)
文件大?。?/td> 1632K
代理商: MCF52277CVM166
MCF5227x ColdFire Microprocessor Data Sheet, Rev. 4
Preliminary—Subject to Change Without Notice
Electrical Characteristics
Freescale Semiconductor
38
Figure 26. SBF Timing
5.17
JTAG and Boundary Scan Timing Specifications
Table 30. SBF AC Timing Specifications
Num
Characteristic
Symbol
Min
Max
Unit
Notes
SB1
SBF_CK Cycle Time
tSBFCK
30
ns
1
1 At reset, the SBF_CK cycle time is t
REF × 67. The first byte of data read from the serial memory contains a divider
value that is used to set the SBF_CK cycle time for the duration of the serial boot process.
SB2
SBF_CK High/Low Time
30%
tSBFCK
SB3
SBF_CS to SBF_CK delay
tSBFCK – 2.0
ns
SB4
SBF_CK to SBF_CS delay
tSBFCK – 2.0
ns
SB5
SBF_CK to SBF_DO valid
12
ns
SB6
SBF_CK to SBF_DO invalid
0
ns
SB7
SBF_DI to SBF_SCK input setup
6
ns
SB8
SBF_CK to SBF_DI input hold
0
ns
Table 31. JTAG and Boundary Scan Timing
Num
Characteristic1
Symbol
Min
Max
Unit
J1
TCLK Frequency of Operation
fJCYC
DC
1/4
fsys/2
J2
TCLK Cycle Period
tJCYC
4—
tCYC
J3
TCLK Clock Pulse Width
tJCW
26
ns
J4
TCLK Rise and Fall Times
tJCRF
03
ns
J5
Boundary Scan Input Data Setup Time to TCLK Rise
tBSDST
4—
ns
J6
Boundary Scan Input Data Hold Time after TCLK Rise
tBSDHT
26
ns
J7
TCLK Low to Boundary Scan Output Data Valid
tBSDV
033
ns
J8
TCLK Low to Boundary Scan Output High Z
tBSDZ
033
ns
SBF_CS
SBF_DO
SBF_DI
Data
Last Data
First Data
Data
Last Data
SBF_CK
SB3
SB1
SB2
SB8
SB7
SB6
SB5
SB4
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