參數(shù)資料
型號(hào)： MCF52277CVM166
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 166.67 MHz, RISC PROCESSOR, PBGA196
封裝： 15 X 15 MM, PLASTIC, ROHS COMPLIANT, MAPBGA-196
文件頁(yè)數(shù)： 17/42頁(yè)
文件大?。?/td> 1632K
代理商： MCF52277CVM166
MCF5227x ColdFire Microprocessor Data Sheet, Rev. 4
Preliminary—Subject to Change Without Notice
Electrical Characteristics
Freescale Semiconductor
24
Table 13. DDR Timing Specifications
Num
Characteristic
Symbol
Min
Max
Unit
Notes
Frequency of Operation
tDDCK
TBD
83.33
MHz
1
1 The frequency of operation is either 2x or 4x the FB_CLK frequency of operation. FlexBus and SDRAM clock operate at the
same frequency as the internal bus clock.
DD1
Clock Period
tDDSK
12.0
TBD
ns
2
2 SD_CLK is one SDRAM clock in ns.
DD2
Pulse Width High
tDDCKH
0.45
0.55
SD_CLK
3
3 Pulse-width high plus pulse-width low cannot exceed minimum or maximum clock period.
DD3
Pulse Width Low
tDDCKL
0.45
0.55
SD_CLK
DD4
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Valid
tSDCHACV
—0.5
× SD_CLK
+1.0
ns
4
4 Command output valid should be one-half the memory bus clock (SD_CLK) plus some minor adjustments for process,
temperature, and voltage variations.
DD5
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Hold
tSDCHACI
2.0
—
ns
DD6
Write Command to first DQS Latching Transition
tCMDVDQ
—
1.25
SD_CLK
DD7
Data and Data Mask Output Setup (DQ
→DQS)
Relative to DQS (DDR Write Mode)
tDQDMV
1.5
—
ns
5
6
5 This specification relates to the required input setup time of today’s DDR memories. The device’s output setup should be larger
than the input setup of the DDR memories. If it is not larger, then the input setup on the memory will be in violation.
MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to
MEM_DQS[1], and MEM_DATA[7:0] is relative MEM_DQS[0].
6 The first data beat will be valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats
will be valid for each subsequent DQS edge.
DD8
Data and Data Mask Output Hold (DQS
→DQ) Relative
to DQS (DDR Write Mode)
tDQDMI
1.0
—
ns
7
7 This specification relates to the required hold time of today’s DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3],
MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_DATA[7:0] is relative
MEM_DQS[0].
DD9
Input Data Skew Relative to DQS (Input Setup)
tDVDQ
—1
ns
8
8 Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line
becomes valid. This input skew must include DDR memory output skew and system-level board skew (due to routing or other
factors).
DD10 Input Data Hold Relative to DQS
tDIDQ
0.25
× SD_CLK
+0.5ns
—ns
9
9 Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line becomes
invalid.
DD11 DQS falling edge from SDCLK rising (output hold time) tDQLSDCH
0.5
—
ns
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