參數(shù)資料
型號(hào)： MCF52277CVM166
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 166.67 MHz, RISC PROCESSOR, PBGA196
封裝： 15 X 15 MM, PLASTIC, ROHS COMPLIANT, MAPBGA-196
文件頁(yè)數(shù)： 14/42頁(yè)
文件大?。?/td> 1632K
代理商： MCF52277CVM166
Electrical Characteristics
MCF5227x ColdFire Microprocessor Data Sheet, Rev. 4
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
21
Figure 8. FlexBus Read Timing
Figure 9. Flexbus Write Timing
5.7.2
SDRAM Bus
The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports either standard
SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time.
5.7.2.1
SDR SDRAM AC Timing Specifications
The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the memory bus
clock, when operating in SDR mode on write cycles and relative to SD_DQS on read cycles. The device’s SDRAM controller
is a DDR controller that has an SDR mode. Because it is designed to support DDR, a DQS pulse must still be supplied to the
device for each data beat of an SDR read. The processor accomplishes this by asserting a signal named SD_SDR_DQS during
FB_CLK
FB_R/W
S0
S1
S2
S3
FB_TS
FB_A[23:0]
FB_D[31:X]
FB_CSn, FB_OE,
FB_BE/BWEn
FB_TA
DATA
ADDR[31:X]
ADDR[23:0]
FB3
FB1
FB2
FB5
FB4
FB7
FB6
FB_CLK
FB_R/W
FB_TS
FB_OE
S0
S2
S3
DATA
S1
ADDR[31:X]
FB_A[23:0]
FB_D[31:X]
ADDR[23:0]
FB_CSn, FB_BE/BWEn
FB_TA
FB3
FB1
FB2
FB7
FB6
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