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參數(shù)資料
| 型號： | MCF52277CVM166 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 166.67 MHz, RISC PROCESSOR, PBGA196 |
| 封裝： | 15 X 15 MM, PLASTIC, ROHS COMPLIANT, MAPBGA-196 |
| 文件頁數(shù)： | 15/42頁 |
| 文件大?。?/td> | 1632K |
| 代理商： | MCF52277CVM166 |
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MCF5227x ColdFire Microprocessor Data Sheet, Rev. 4
Preliminary—Subject to Change Without Notice
Electrical Characteristics
Freescale Semiconductor
22
read cycles. Care must be taken during board design to adhere to the following guidelines and specs with regard to the
SD_SDR_DQS signal and its usage.
Table 12. SDR Timing Specifications
Num
Characteristic
Symbol
Min
Max
Unit
Notes
Frequency of Operation
TBD
83.33
MHz
1
1 The device supports same frequency of operation for both FlexBus and SDRAM clock operates as that of the internal bus clock.
Please see the PLL chapter of the device reference manual for more information on setting the SDRAM clock rate.
SD1 Clock Period
tSDCK
12.0
TBD
ns
2
2 SD_CLK is one SDRAM clock in ns.
SD2 Pulse Width High
tSDCKH
0.45
0.55
SD_CLK
3
3 Pulse width high plus pulse width low cannot exceed min and max clock period.
SD3 Pulse Width Low
tSDCKH
0.45
0.55
SD_CLK
SD4 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] - Output Valid
tSDCHACV
—0.5
× SD_CLK
+1.0
ns
SD5 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] - Output Hold
tSDCHACI
2.0
—
ns
SD6 SD_SDR_DQS Output Valid
tDQSOV
—Self timed
ns
4
4 SD_SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle
variation from this guideline is expected. SD_SDR_DQS will only pulse during a read cycle and one pulse will occur for each
data beat.
SD7 SD_DQS[3:2] input setup relative to SD_CLK
tDQVSDCH
0.25
×
SD_CLK
0.40
× SD_CLK
ns
5
5 SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle
variation from this guideline is expected. SD_DQS will only pulse during a read cycle and one pulse will occur for each data
beat.
SD8 SD_DQS[3:2] input hold relative to SD_CLK
tDQISDCH
Does not apply. 0.5
×SD_CLK fixed
width.
6
6 The SD_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge does
not affect the memory controller.
SD9 Data (D[31:0]) Input Setup relative to SD_CLK (reference
only)
tDVSDCH
0.25
×
SD_CLK
—ns
7
7 Since a read cycle in SDR mode still uses the DQS circuit within the device, it is critical that the data valid window be centered
1/4 clk after the rising edge of DQS. Ensuring that this happens will result in successful SDR reads. The input setup spec is
provided as guidance.
SD10 Data Input Hold relative to SD_CLK (reference only)
tDISDCH
1.0
—
ns
SD11 Data (D[31:0]) and Data Mask(SD_DQM[3:0]) Output Valid
tSDCHDMV
—0.5
× SD_CLK
+ 2
ns
SD12 Data (D[31:0]) and Data Mask (SD_DQM[3:0]) Output Hold
tSDCHDMI
1.5
—
ns
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| MCF5232CAB80 | 功能描述:微處理器 - MPU MCF5232 V2CORE 64KSRAM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MCF5232CVM100 | 功能描述:微處理器 - MPU MCF5232 V2CORE 64KSRAM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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