參數(shù)資料
型號: MC9328MXSVP10R2
廠商: Freescale Semiconductor
文件頁數(shù): 71/74頁
文件大?。?/td> 0K
描述: IC MCU I.MXS 100MHZ 225-MAPBGA
標(biāo)準(zhǔn)包裝: 1,000
系列: i.MXS
核心處理器: ARM9
芯體尺寸: 32-位
速度: 100MHz
連通性: EBI/EMI,I²C,SPI,SSI,UART/USART,USB
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 97
程序存儲(chǔ)器類型: ROMless
電壓 - 電源 (Vcc/Vdd): 1.7 V ~ 3.3 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 225-LFBGA
包裝: 帶卷 (TR)
Product Documentation
MC9328MXS Technical Data, Rev. 3
Freescale Semiconductor
73
6
Product Documentation
6.1
Revision History
Table 32 provides revision history for this release. This history includes technical content revisions only
and not stylistic or grammatical changes.
6.2
Reference Documents
The following documents are required for a complete description of the MC9328MXS and are necessary
to design properly with the device. Especially for those not familiar with the ARM920T processor or
previous i.MX processor products, the following documents are helpful when used in conjunction with this
document.
ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100)
ARM9DT1 Data Sheet Manual (ARM Ltd., order number ARM DDI 0029)
ARM Technical Reference Manual (ARM Ltd., order number ARM DDI 0151C)
EMT9 Technical Reference Manual (ARM Ltd., order number DDI O157E)
MC9328MXS Product Brief (order number MC9328MXSP)
MC9328MXS Reference Manual (order number MC9328MXSRM)
The Freescale manuals are available on the Freescale Semiconductors Web site at
http://www.freescale.com/imx. These documents may be downloaded directly from the Freescale Web
site, or printed versions may be ordered. The ARM Ltd. documentation is available from
http://www.arm.com.
Table 32. i.MXS Data Sheet Revision History Rev. 3
Location
Revision
Signal Names and
Descriptions
Added the DMA_REQ signal to table.
Corrected signal name from USBD_OE to USBD_ROE
Signal Multiplex Table i.MXS
Added Signal Multiplex table from Reference Manual with the following changes:
Corrected BGA pin assignments.
Changed first and second parameters descriptions:
From: Reference Clock freq range, To: DPLL input clock freq range
From: Double clock freq range, To: DPLL output freq range
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