參數(shù)資料
型號(hào): MC9328MXSVP10R2
廠商: Freescale Semiconductor
文件頁數(shù): 22/74頁
文件大?。?/td> 0K
描述: IC MCU I.MXS 100MHZ 225-MAPBGA
標(biāo)準(zhǔn)包裝: 1,000
系列: i.MXS
核心處理器: ARM9
芯體尺寸: 32-位
速度: 100MHz
連通性: EBI/EMI,I²C,SPI,SSI,UART/USART,USB
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 97
程序存儲(chǔ)器類型: ROMless
電壓 - 電源 (Vcc/Vdd): 1.7 V ~ 3.3 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 225-LFBGA
包裝: 帶卷 (TR)
Functional Description and Application Information
MC9328MXS Technical Data, Rev. 3
Freescale Semiconductor
29
4.4.3
EIM External Bus Timing
The External Interface Module (EIM) is the interface to devices external to the i.MXS, including generation
of chip-selects for external peripherals and memory. The timing diagram for the EIM is shown in Figure 5,
and Table 12 defines the parameters of signals.
Table 16. WAIT Write Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
Number
Characteristic
3.0 ± 0.3 V
Unit
Minimum
Maximum
1
CS5 assertion time
See note 2
ns
2EB assertion time
See note 2
ns
3CS5 pulse width
3T
ns
4RW negated before CS5 is negated
2.5T-3.63
2.5T-1.16
ns
5
Address inactived after CS negated
0.09
ns
6
Wait asserted after CS5 asserted
1020T
ns
7
Wait asserted to RW negated
T+2.66
2T+7.96
ns
8
Data hold timing after RW negated
2T+0.03
ns
9
Data ready after CS5 is asserted
T
ns
10
CS deactive to next CS active
T
ns
11
EB negate after CS negate
0.5T
0.5T+0.5
12
Wait becomes low after CS5 asserted
0
1019T
ns
13
Wait pulse width
1T
1020T
ns
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
2. CS5 assertion can be controlled by CSA bits. EB assertion also can be programmable by WEA bits in CS5L register.
3. Address becomes valid and RW asserts at the start of write access cycle.
4.The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
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