參數(shù)資料
型號(hào)： MC9328MXSVP10
廠商： Freescale Semiconductor
文件頁數(shù)： 8/74頁
文件大?。?/td> 0K
描述： IC MCU I.MXS 100MHZ 225-MAPBGA
標(biāo)準(zhǔn)包裝： 160
系列： i.MXS
核心處理器： ARM9
芯體尺寸： 32-位
速度： 100MHz
連通性： EBI/EMI，I²C，SPI，SSI，UART/USART，USB
外圍設(shè)備： DMA，I²S，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 97
程序存儲(chǔ)器類型： ROMless
電壓 - 電源 (Vcc/Vdd)： 1.7 V ~ 3.3 V
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 225-LFBGA
包裝： 托盤
Electrical Characteristics
MC9328MXS Technical Data, Rev. 3
16
Freescale Semiconductor
3
Electrical Characteristics
This section contains the electrical specifications and timing diagrams for the i.MXS processor.
3.1
Maximum Ratings
Table 4 provides information on maximum ratings which are those values beyond which damage to the
device may occur. Functional operation should be restricted to the limits listed in Recommended Operating
Range Table 5 on page 17 or the DC Characteristics table.
3.2
Recommended Operating Range
Table 5 provides the recommended operating ranges for the supply voltages and temperatures. The i.MXS
processor has multiple pairs of VDD and VSS power supply and return pins. QVDD and QVSS pins are
used for internal logic. All other VDD and VSS pins are for the I/O pads voltage supply, and each pair of
VDD and VSS provides power to the enclosed I/O pads. This design allows different peripheral supply
voltage levels in a system.
Because AVDD pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter
the AVDD pins from other VDD pins.
For more information about I/O pads grouping per VDD, please refer to Table 2 on page 4.
Table 4. Maximum Ratings
Symbol
Rating
Minimum
Maximum
Unit
NVDD
DC I/O Supply Voltage
-0.3
3.3
V
QVDD
DC Internal (core = 100 MHz) Supply Voltage
-0.3
1.9
V
AVDD
DC Analog Supply Voltage
-0.3
3.3
V
BTRFVDD
DC Bluetooth Supply Voltage
-0.3
3.3
V
VESD_HBM
ESD immunity with HBM (human body model)
–
2000
V
VESD_MM
ESD immunity with MM (machine model)
–
100
V
ILatchup
Latch-up immunity
–
200
mA
Test
Storage temperature
-55
150
°C
Pmax
Power Consumption
8001
1 A typical application with 30 pads simultaneously switching assumes the GPIO toggling and instruction fetches from the ARM
core-that is, 7x GPIO, 15x Data bus, and 8x Address bus.
13002
2 A worst-case application with 70 pads simultaneously switching assumes the GPIO toggling and instruction fetches from the
ARM core-that is, 32x GPIO, 30x Data bus, 8x Address bus. These calculations are based on the core running its heaviest OS
application at 100MHz, and where the whole image is running out of SDRAM. QVDD at 1.9V, NVDD and AVDD at 3.3V,
therefore, 180mA is the worst measurement recorded in the factory environment, max 5mA is consumed for OSC pads, with
each toggle GPIO consuming 4mA.
mW
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參數(shù)描述
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