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| 型號： | MC9328MXSVP10 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 34/74頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU I.MXS 100MHZ 225-MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | i.MXS |
| 核心處理器： | ARM9 |
| 芯體尺寸： | 32-位 |
| 速度： | 100MHz |
| 連通性： | EBI/EMI，I²C，SPI，SSI，UART/USART，USB |
| 外圍設(shè)備： | DMA，I²S，LCD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 97 |
| 程序存儲(chǔ)器類型： | ROMless |
| 電壓 - 電源 (Vcc/Vdd)： | 1.7 V ~ 3.3 V |
| 振蕩器型： | 外部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 225-LFBGA |
| 包裝： | 托盤 |
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Signals and Connections
MC9328MXS Technical Data, Rev. 3
4
Freescale Semiconductor
2
Signals and Connections
Table 2 identifies and describes the i.MXS processor signals that are assigned to package pins. The signals
are grouped by the internal module that they are connected to.
Table 2. i.MXS Signal Descriptions
Signal Name
Function/Notes
External Bus/Chip-Select (EIM)
A[24:0]
Address bus signals
D[31:0]
Data bus signals
EB0
MSB Byte Strobe—Active low external enable byte signal that controls D [31:24].
EB1
Byte Strobe—Active low external enable byte signal that controls D [23:16].
EB2
Byte Strobe—Active low external enable byte signal that controls D [15:8].
EB3
LSB Byte Strobe—Active low external enable byte signal that controls D [7:0].
OE
Memory Output Enable—Active low output enables external data bus.
CS [5:0]
Chip-Select—The chip-select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the
Function Multiplexing Control Register (FMCR). By default CSD [1:0] is selected.
ECB
Active low input signal sent by a flash device to the EIM whenever the flash device must terminate an
on-going burst sequence and initiate a new (long first access) burst sequence.
LBA
Active low signal sent by a flash device causing the external burst device to latch the starting burst
address.
BCLK (burst clock)
Clock signal sent to external synchronous memories (such as burst flash) during burst mode.
RW
RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used as a WE input
signal by external DRAM.
DTACK
DTACK signal—The external input data acknowledge signal. When using the external DTACK signal
as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not
terminated by the external DTACK signal after 1022 clock counts have elapsed.
Bootstrap
BOOT [3:0]
System Boot Mode Select—The operational system boot mode of the i.MXS processor upon system
reset is determined by the settings of these pins.
SDRAM Controller
SDBA [4:0]
SDRAM non-interleave mode bank address multiplexed with address signals A [15:11]. These signals
are logically equivalent to core address p_addr [25:21] in SDRAM cycles.
SDIBA [3:0]
SDRAM interleave addressing mode bank address multiplexed with address signals A [19:16]. These
signals are logically equivalent to core address p_addr [12:9] in SDRAM cycles.
MA [11:10]
SDRAM address signals
MA [9:0]
SDRAM address signals which are multiplexed with address signals A [10:1]. MA [9:0] are selected on
SDRAM cycles.
DQM [3:0]
SDRAM data enable
CSD0
SDRAM Chip-select signal which is multiplexed with the CS2 signal. These two signals are selectable
by programming the system control register.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MC9328MXSVP10 | 制造商:Freescale Semiconductor 功能描述:Microprocessor |
| MC9328MXSVP10R2 | 功能描述:處理器 - 專門應(yīng)用 REDUCED FEATURE CORSICA RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
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| MC933 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:INTEGRATED CIRCUITS |
| MC933F | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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