參數(shù)資料
型號: MC9328MXLVF15
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 150 MHz, RISC PROCESSOR, PBGA225
封裝: 13 X 13 MM, 0.80 MM PITCH, MAPBGA-225
文件頁數(shù): 69/89頁
文件大小: 1869K
代理商: MC9328MXLVF15
Specifications
MOTOROLA
MC9328MXL Advance Information
71
28
STCK high to STXD high impedance
18.47
28.5
16.2
25.0
ns
29
SRXD setup time before SRCK low
1.14
1.0
ns
30
SRXD hole time after SRCK low
0
0
ns
Synchronous Internal Clock Operation (Port C Primary Function2)
31
SRXD setup before STCK falling
15.4
13.5
ns
32
SRXD hold after STCK falling
0
0—
ns
Synchronous External Clock Operation (Port C Primary Function2)
33
SRXD setup before STCK falling
1.14
1.0
ns
34
SRXD hold after STCK falling
0
0—
ns
1.
All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a
non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync
STFS/SRFS shown in the tables and in the figures.
2.
There are 2 sets of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad
261) and Port B alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they
can be viewed both at Port C primary function and Port B alternate function. When SSI signals are
configured as input, the SSI module selects the input based on status of the FMCR register bits in the
Clock controller module (CRM). By default, the input are selected from Port C primary function.
3.
bl = bit length; wl = word length.
Table 29. SSI (Port B Alternate Function) Timing Parameter Table
Ref
No.
Parameter
1.8V ± 0.10V
3.0V ± 0.30V
Unit
Minimum
Maximum
Minimum
Maximum
Internal Clock Operation1 (Port B Alternate Function2)
1
STCK/SRCK clock period1
95
83.3
ns
2
STCK high to STFS (bl) high3
1.7
4.8
1.5
4.2
ns
3
SRCK high to SRFS (bl) high3
-0.1
1.0
-0.1
1.0
ns
4
STCK high to STFS (bl) low3
3.08
5.24
2.7
4.6
ns
5
SRCK high to SRFS (bl) low3
1.25
2.28
1.1
2.0
ns
6
STCK high to STFS (wl) high3
1.71
4.79
1.5
4.2
ns
7
SRCK high to SRFS (wl) high3
-0.1
1.0
-0.1
1.0
ns
8
STCK high to STFS (wl) low3
3.08
5.24
2.7
4.6
ns
Table 28. SSI (Port C Primary Function) Timing Parameter Table (Continued)
Ref No.
Parameter
1.8V ± 0.10V
3.0V ± 0.30V
Unit
Minimum
Maximum
Minimum
Maximum
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