
6
MC9328MXL Advance Information
MOTOROLA
Signals and Connections
CAS
SDRAM/SyncFlash Column Address Select signal
SDWE
SDRAM/SyncFlash Write Enable signal
SDCKE0
SDRAM/SyncFlash Clock Enable 0
SDCKE1
SDRAM/SyncFlash Clock Enable 1
SDCLK
SDRAM/SyncFlash Clock
RESET_SF
SyncFlash Reset
Clocks and Resets
EXTAL16M
Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when the internal oscillator
circuit is shut down.
XTAL16M
Crystal output
EXTAL32K
32 kHz crystal input
XTAL32K
32 kHz crystal output
CLKO
Clock Out signal selected from internal clock signals.
RESET_IN
Master Reset—External active low Schmitt trigger input signal. When this signal goes
active, all modules (except the reset module and the clock control module) are reset.
RESET_OUT
Reset Out—Internal active low output signal from the Watchdog Timer module and is
asserted from the following sources: Power-on reset, External reset (RESET_IN), and
Watchdog time-out.
POR
Power On Reset—Internal active high Schmitt trigger input signal. The POR signal is
normally generated by an external RC circuit designed to detect a power-up event.
JTAG
TRST
Test Reset Pin—External active low signal used to asynchronously initialize the JTAG
controller.
TDO
Serial Output for test instructions and data. Changes on the falling edge of TCK.
TDI
Serial Input for test instructions and data. Sampled on the rising edge of TCK.
TCK
Test Clock to synchronize test logic and control register access through the JTAG port.
TMS
Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the
rising edge of TCK.
DMA
BIG_ENDIAN
Big Endian—Input signal that determines the configuration of the external chip-select
space. If it is driven logic-high at reset, the external chip-select space will be configured to
little endian. If it is driven logic-low at reset, the external chip-select space will be
configured to big endian.
DMA_REQ
External DMA request pin.
Table 2. MC9328MXL Signal Descriptions (Continued)
Signal Name
Function/Notes