參數(shù)資料
型號(hào)： MC9328MXLVF15
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 150 MHz, RISC PROCESSOR, PBGA225
封裝： 13 X 13 MM, 0.80 MM PITCH, MAPBGA-225
文件頁(yè)數(shù)： 45/89頁(yè)
文件大?。?/td> 1869K
代理商： MC9328MXLVF15
Signals and Connections
MOTOROLA
MC9328MXL Advance Information
5
EB1
Byte Strobe—Active low external enable byte signal that controls D [23:16].
EB2
Byte Strobe—Active low external enable byte signal that controls D [15:8].
EB3
LSB Byte Strobe—Active low external enable byte signal that controls D [7:0].
OE
Memory Output Enable—Active low output enables external data bus.
CS [5:0]
Chip-Select—The chip-select signals CS [3:2] are multiplexed with CSD [1:0] and are
selected by the Function Multiplexing Control Register (FMCR). By default CSD [1:0] is
selected.
ECB
Active low input signal sent by a flash device to the EIM whenever the flash device must
terminate an on-going burst sequence and initiate a new (long first access) burst
sequence.
LBA
Active low signal sent by a flash device causing the external burst device to latch the
starting burst address.
BCLK
Clock signal sent to external synchronous memories (such as burst flash) during burst
mode.
RW
RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used
as a WE input signal by external DRAM.
DTACK
DTACK signal— The external input data acknowledge signal. When using the external
DTACK signal as a data acknowledge signal, the bus time-out monitor generates a bus
error when a bus cycle is not terminated by the external DTACK signal after 1022 clock
counts have elapsed.
Bootstrap
BOOT [3:0]
System Boot Mode Select—The operational system boot mode of the MC9328MXL upon
system reset is determined by the settings of these pins.
SDRAM Controller
SDBA [4:0]
SDRAM/SyncFlash non-interleave mode bank address multiplexed with address signals
A [15:11]. These signals are logically equivalent to core address p_addr [25:21] in
SDRAM/SyncFlash cycles.
SDIBA [3:0]
SDRAM/SyncFlash interleave addressing mode bank address multiplexed with address
signals A [19:16]. These signals are logically equivalent to core address p_addr [12:9] in
SDRAM/SyncFlash cycles.
MA [11:10]
SDRAM address signals
MA [9:0]
SDRAM address signals which are multiplexed with address signals A [10:1]. MA [9:0]
are selected on SDRAM/SyncFlash cycles.
DQM [3:0]
SDRAM data enable
CSD0
SDRAM/SyncFlash Chip-select signal which is multiplexed with the CS2 signal. These
two signals are selectable by programming the system control register.
CSD1
SDRAM/SyncFlash Chip-select signal which is multiplexed with CS3 signal. These two
signals are selectable by programming the system control register. By default, CSD1 is
selected, so it can be used as SyncFlash boot chip-select by properly configuring BOOT
[3:0] input pins.
RAS
SDRAM/SyncFlash Row Address Select signal
Table 2. MC9328MXL Signal Descriptions (Continued)
Signal Name
Function/Notes
相關(guān)PDF資料
PDF描述
MC9328MXLVH20 32-BIT, 200 MHz, RISC PROCESSOR, PBGA256
MC9328MXLDVM20 200 MHz, RISC PROCESSOR, PBGA256
MC9328MXLVM20 200 MHz, RISC PROCESSOR, PBGA256
MC9328MXLVP20 200 MHz, RISC PROCESSOR, PBGA225
MC9328MXLVH20R2 32-BIT, 200 MHz, RISC PROCESSOR, PBGA256
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC9328MXLVF20 制造商:Rochester Electronics LLC 功能描述:DRAGONBALL CORSICA 225 - Bulk 制造商:Motorola Inc 功能描述:
MC9328MXLVF20R2 制造商:Rochester Electronics LLC 功能描述:DRAGONBALL CORSICA 225 - Bulk
MC9328MXLVH15 制造商:FREESCALE-SEMI 功能描述:
MC9328MXLVH20 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:i.MX Integrated Portable System Processor
MC9328MXLVH20R2 制造商:Rochester Electronics LLC 功能描述:DRAGONBALL CORSICA - Bulk 制造商:Motorola Inc 功能描述:
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