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參數(shù)資料
| 型號： | MC9328MXLDVP20R2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 56/90頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU I.MX 200MHZ 225-MAPBGA |
| 標準包裝： | 1,000 |
| 系列： | i.MXL |
| 核心處理器： | ARM9 |
| 芯體尺寸： | 32-位 |
| 速度： | 200MHz |
| 連通性： | EBI/EMI，I²C，MMC/SD，SPI，SSI，UART/USART，USB |
| 外圍設(shè)備： | DMA，I²S，LCD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 97 |
| 程序存儲器類型： | ROMless |
| 電壓 - 電源 (Vcc/Vdd)： | 1.7 V ~ 3.3 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -30°C ~ 70°C |
| 封裝/外殼： | 225-LFBGA |
| 包裝： | 帶卷 (TR) |
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Signals and Connections
MC9328MXL Technical Data, Rev. 8
6
Freescale Semiconductor
JTAG
TRST
Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.
TDO
Serial Output for test instructions and data. Changes on the falling edge of TCK.
TDI
Serial Input for test instructions and data. Sampled on the rising edge of TCK.
TCK
Test Clock to synchronize test logic and control register access through the JTAG port.
TMS
Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge of
TCK.
DMA
DMA_REQ
DMA Request—external DMA request signal. Multiplexed with SPI1_SPI_RDY.
BIG_ENDIAN
Big Endian—Input signal that determines the configuration of the external chip-select space. If it is
driven logic-high at reset, the external chip-select space will be configured to big endian. If it is driven
logic-low at reset, the external chip-select space will be configured to little endian. This input must not
change state after power-on reset negates or during chip operation.
ETM
ETMTRACESYNC
ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode.
ETMTRACECLK
ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode.
ETMPIPESTAT [2:0]
ETM status signals which are multiplexed with A [22:20]. ETMPIPESTAT [2:0] are selected in ETM
mode.
ETMTRACEPKT [7:0] ETM packet signals which are multiplexed with ECB, LBA, BCLK (burst clock), PA17, A [19:16].
ETMTRACEPKT [7:0] are selected in ETM mode.
CMOS Sensor Interface
CSI_D [7:0]
Sensor port data
CSI_MCLK
Sensor port master clock
CSI_VSYNC
Sensor port vertical sync
CSI_HSYNC
Sensor port horizontal sync
CSI_PIXCLK
Sensor port data latch clock
LCD Controller
LD [15:0]
LCD Data Bus—All LCD signals are driven low after reset and when LCD is off.
FLM/VSYNC
Frame Sync or Vsync—This signal also serves as the clock signal output for the gate
driver (dedicated signal SPS for Sharp panel HR-TFT).
LP/HSYNC
Line pulse or H sync
LSCLK
Shift clock
ACD/OE
Alternate crystal direction/output enable.
CONTRAST
This signal is used to control the LCD bias voltage as contrast control.
SPL_SPR
Program horizontal scan direction (Sharp panel dedicated signal).
PS
Control signal output for source driver (Sharp panel dedicated signal).
Table 2. i.MXL Signal Descriptions (Continued)
Signal Name
Function/Notes
相關(guān)PDF資料 |
PDF描述 |
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| VI-B2L-IY-F1 | CONVERTER MOD DC/DC 28V 50W |
| VI-B2K-IY-F4 | CONVERTER MOD DC/DC 40V 50W |
| VI-B2J-IY-F2 | CONVERTER MOD DC/DC 36V 50W |
| VI-B2H-IY-F2 | CONVERTER MOD DC/DC 52V 50W |
| MC68HC16Z1CAG16 | IC MCU 16BIT 16MHZ 144-LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC9328MXLP/D | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:i.MX Integrated Portable System Processor |
| MC9328MXLRM/D | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:i.MX Integrated Portable System Processor |
| MC9328MXLVF20 | 制造商:Rochester Electronics LLC 功能描述:DRAGONBALL CORSICA 225 - Bulk 制造商:Motorola Inc 功能描述: |
| MC9328MXLVF20R2 | 制造商:Rochester Electronics LLC 功能描述:DRAGONBALL CORSICA 225 - Bulk |
| MC9328MXLVH15 | 制造商:FREESCALE-SEMI 功能描述: |
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