參數(shù)資料
型號： MC9328MXLDVP20R2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA225
封裝： 13 X 13 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, MAPBGA-225
文件頁數(shù)： 56/90頁
文件大?。?/td> 1242K
代理商： MC9328MXLDVP20R2
Signals and Connections
MC9328MXL Technical Data, Rev. 8
6
Freescale Semiconductor
JTAG
TRST
Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.
TDO
Serial Output for test instructions and data. Changes on the falling edge of TCK.
TDI
Serial Input for test instructions and data. Sampled on the rising edge of TCK.
TCK
Test Clock to synchronize test logic and control register access through the JTAG port.
TMS
Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge of
TCK.
DMA
DMA_REQ
DMA Request—external DMA request signal. Multiplexed with SPI1_SPI_RDY.
BIG_ENDIAN
Big Endian—Input signal that determines the configuration of the external chip-select space. If it is
driven logic-high at reset, the external chip-select space will be configured to big endian. If it is driven
logic-low at reset, the external chip-select space will be configured to little endian. This input must not
change state after power-on reset negates or during chip operation.
ETM
ETMTRACESYNC
ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode.
ETMTRACECLK
ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode.
ETMPIPESTAT [2:0]
ETM status signals which are multiplexed with A [22:20]. ETMPIPESTAT [2:0] are selected in ETM
mode.
ETMTRACEPKT [7:0] ETM packet signals which are multiplexed with ECB, LBA, BCLK (burst clock), PA17, A [19:16].
ETMTRACEPKT [7:0] are selected in ETM mode.
CMOS Sensor Interface
CSI_D [7:0]
Sensor port data
CSI_MCLK
Sensor port master clock
CSI_VSYNC
Sensor port vertical sync
CSI_HSYNC
Sensor port horizontal sync
CSI_PIXCLK
Sensor port data latch clock
LCD Controller
LD [15:0]
LCD Data Bus—All LCD signals are driven low after reset and when LCD is off.
FLM/VSYNC
Frame Sync or Vsync—This signal also serves as the clock signal output for the gate
driver (dedicated signal SPS for Sharp panel HR-TFT).
LP/HSYNC
Line pulse or H sync
LSCLK
Shift clock
ACD/OE
Alternate crystal direction/output enable.
CONTRAST
This signal is used to control the LCD bias voltage as contrast control.
SPL_SPR
Program horizontal scan direction (Sharp panel dedicated signal).
PS
Control signal output for source driver (Sharp panel dedicated signal).
Table 2. i.MXL Signal Descriptions (Continued)
Signal Name
Function/Notes
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MXL
Product
Family
相關PDF資料
PDF描述
MC9328MXLDVM20R2 32-BIT, 200 MHz, RISC PROCESSOR, PBGA256
MC9328MXLDVM15 150 MHz, RISC PROCESSOR, PBGA256
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MC9328MXLDVP15 150 MHz, RISC PROCESSOR, PBGA225
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