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參數(shù)資料
| 型號： | MC9328MXLDVP20R2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA225 |
| 封裝： | 13 X 13 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, MAPBGA-225 |
| 文件頁數(shù)： | 22/90頁 |
| 文件大?。?/td> | 1242K |
| 代理商： | MC9328MXLDVP20R2 |
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Functional Description and Application Information
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
29
4.4.2.4
WAIT Write Cycle DMA Enabled
Figure 9. WAIT Write Cycle DMA Enabled
7
Wait asserted to RW negated
T+2.66
2T+7.96
ns
8
Data hold timing after RW negated
2T+0.03
–
ns
9
Data ready after CS5 is asserted
–
T
ns
10
EB negated after CS5 is negated
0.5T
0.5T+0.5
ns
11
Wait becomes low after CS5 asserted
0
1019T
ns
12
Wait pulse width
1T
1020T
ns
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
2. CS5 assertion can be controlled by CSA bits. EB assertion can also be programmable by WEA bits in CS5L register.
3. Address becomes valid and RW asserts at the start of write access cycle.
4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
Table 15. WAIT Write Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz (Continued)
Number
Characteristic
3.0 ± 0.3 V
Unit
Minimum
Maximum
OE
WAIT
Address
EB
CS5
RW
(logic high)
DATABUS
programmable
min 0ns
programmable
min 0ns
8
5
7
11
12
4
1
2
3
10
6
13
9
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MXL
Product
Family
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