參數(shù)資料
型號: MC9328MX1VM20R2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 200 MHz, RISC PROCESSOR, PBGA256
封裝: 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, MAPBGA-256
文件頁數(shù): 68/94頁
文件大?。?/td> 1487K
代理商: MC9328MX1VM20R2
70
MC9328MX1 Advance Information
MOTOROLA
Specifications
3.16 Pulse-Width Modulator
The PWM can be programmed to select one of two clock signals as its source frequency. The selected
clock signal is passed through a divider and a prescaler before being input to the counter. The output is
available at the pulse-width modulator output (PWMO) external pin.
Figure 56. PWM Output Timing Diagram
12
MS_SDIO output delay time1,2
–3
ns
13
MS_SDIO input setup time for MS_SCLKO rising edge (RED bit = 0)3
18
ns
14
MS_SDIO input hold time for MS_SCLKO rising edge (RED bit = 0)3
0–
ns
15
MS_SDIO input setup time for MS_SCLKO falling edge (RED bit =
1)4
23
ns
16
MS_SDIO input hold time for MS_SCLKO falling edge (RED bit = 1)4
0–
ns
1.
Loading capacitor condition is less than or equal to 30pF.
2.
An external resistor (100 ~ 200 ohm) should be inserted in series to provide current control on the
MS_SDIO pin, because of a possibility of signal conflict between the MS_SDIO pin and Memory Stick
SDIO pin when the pin direction changes.
3.
If the MSC2[RED] bit = 0, MSHC samples MS_SDIO input data at MS_SCLKO rising edge.
4.
If the MSC2[RED] bit = 1, MSHC samples MS_SDIO input data at MS_SCLKO falling edge.
Table 33. PWM Output Timing Parameter Table
Ref
No.
Parameter
1.8V +/- 0.10V
3.0V +/- 0.30V
Unit
Minimum
Maximum
Minimum
Maximum
1
System CLK frequency1
0870
100
MHz
2a
Clock high time1
3.3
5/10
ns
2b
Clock low time1
7.5
5/10
ns
3a
Clock fall time1
–5
5/10
ns
3b
Clock rise time1
6.67–5/10
ns
Table 32. MSHC Signal Timing Parameter Table (Continued)
Ref No.
Parameter
Minimum
Maximum
Unit
System Clock
2a
1
PWM Output
3b
2b
3a
4b
4a
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