參數(shù)資料
型號(hào)： MC9328MX1VM20R2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 200 MHz, RISC PROCESSOR, PBGA256
封裝： 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, MAPBGA-256
文件頁數(shù)： 16/94頁
文件大小： 1487K
代理商： MC9328MX1VM20R2
Specifications
MOTOROLA
MC9328MX1 Advance Information
23
3.8.1 DTACK Signal Description
The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal
as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not
terminated by the external DTACK signal after 1022 HCLK counts have elapsed Only CS5 group supports
DTACK signal function when using the external DTACK signal for data acknowledgement.
3.8.2 DTACK Signal Timing
Figure 6 through Figure 9 show the access cycle timing used by chip-select 5. The signal values and units
of measure for this figure are found in the associated tables.
3.8.2.1 DTACK READ Cycle without DMA
Figure 6. DTACK READ Cycle without DMA
Table 14. Parameters for Read Cycle, WSC = 111111, DTACK_SEL=0, HKCL=96MHz
Number
Characteristic
(3.0 ± 0.3) V
Unit
Minimum
Maximum
1OE and EB assertion time
See note 2
–
ns
2CS5 pulse width
3T
–
ns
3OE negated to address inactive
46.44
–
ns
4
DTACK asserted after CS5 asserted
–
1019T
ns
5
DTACK asserted to OE negated
3T+2.2
4T+6.86
ns
6
Data hold timing after OE negated
0
–
ns
DTACK
Address
EB
CS5
OE
Databus
programmable
min 0ns
(1)
(5)
(6)
(3)
(2)
(4)
(7)
(input to MX1)
(8)
(9)
(10)
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