參數(shù)資料
型號(hào): MC9328MX1VM20R2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 200 MHz, RISC PROCESSOR, PBGA256
封裝: 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, MAPBGA-256
文件頁(yè)數(shù): 5/94頁(yè)
文件大?。?/td> 1487K
代理商: MC9328MX1VM20R2
Specifications
MOTOROLA
MC9328MX1 Advance Information
13
3 Specifications
This section contains the electrical specifications and timing diagrams for the MC9328MX1 processor.
3.1 Maximum Ratings
Table 4 provides information on maximum ratings.
3.2 Recommended Operating Range
Table 5 provides the recommended operating ranges for the supply voltages. The MC9328MX1 processor
has multiple pairs of VDD and VSS power supply and return pins. QVDD and QVSS pins are used for
internal logic. All other VDD and VSS pins are for the I/O pads voltage supply, and each pair of VDD and
VSS provides power to the enclosed I/O pads. This design allows different peripheral supply voltage levels
in a system.
Because AVDD pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter
the AVDD pins from other VDD pins.
BTRFVDD is the supply voltage for the Bluetooth interface signals. It is quite sensitive to the data
transmit/receive accuracy. Please refer to Bluetooth RF spec for special handling. If Bluetooth is not used
in the system, these Bluetooth pins can be used as general purpose I/O pins and BTRFVDD can be used as
other NVDD pins.
Table 4. Maximum Ratings
Rating
Symbol
Minimum
Maximum
Unit
Supply voltage
Vdd
-0.3
3.3
V
Maximum operating temperature range
MC9328MX1VH20/MC9328MX1VM20
TA
070
°C
Maximum operating temperature range
MC9328MX1DVH20/MC9328MX1DVM20
TA
-30
70
°C
Maximum operating temperature range
MC9328MX1CVH15/MC9328MX1CVM15
TA
-40
85
°C
ESD at human body model (HBM)
VESD_HBM
2000
V
ESD at machine model (MM)
VESD_MM
100
V
Latch-up current
ILatchup
200
mA
Storage temperature
Test
-55
150
°C
Power Consumption
Pmax
8001
1.
A typical application with 30 pads simultaneously switching assumes the GPIO toggling and instruction
fetches from the ARM core-that is, 7x GPIO, 15x Data bus, and 8x Address bus.
13002
2.
A worst-case application with 70 pads simultaneously switching assumes the GPIO toggling and
instruction fetches from the ARM core-that is, 32x GPIO, 30x Data bus, 8x Address bus. These
calculations are based on the core running its heaviest OS application at 200MHz, and where the whole
image is running out of SDRAM. QVDD at 2.0V, NVDD and AVDD at 3.3V, therefore, 180mA is the worst
measurement recorded in the factory environment, max 5mA is consumed for OSC pads, with each toggle
GPIO consuming 4mA.
mW
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