參數(shù)資料
型號: MC9328MX1VM20R2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 200 MHz, RISC PROCESSOR, PBGA256
封裝: 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, MAPBGA-256
文件頁數(shù): 58/94頁
文件大小: 1487K
代理商: MC9328MX1VM20R2
Specifications
MOTOROLA
MC9328MX1 Advance Information
61
3.14 Multimedia Card/Secure Digital Host Controller
The DMA interface block controls all data routing between the external data bus (DMA access), internal
MMC/SD module data bus, and internal system FIFO access through a dedicated state machine that
monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters for the MMC/
SD module (inner system) and the application (user programming).
Figure 47. Chip-Select Read Cycle Timing Diagram
T10
VSYN to OE active (Sharp = 0),
when VWAIT2 = 0
11
Ts
T10
VSYN to OE active (Sharp = 1),
when VWAIT2 = 0
22
Ts
Note:
Ts is the SCLK period which equals LCDC_CLK / (PCD + 1). Normally LCDC_CLK = 15ns.
VSYN, HSYN and OE can be programmed as active high or active low. In Figure 46, all 3 signals are active low.
The polarity of SCLK and LD[15:0] can also be programmed.
SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period. In Figure 46, SCLK is
always active.
For T9 non-display region, VSYN is non-active. It is used as an reference.
XMAX is defined in pixels.
Table 29. SDHC Bus Timing Parameter Table
Ref
No.
Parameter
1.8V +/- 0.10V
3.0V +/- 0.30V
Unit
Min
Max
Min
Max
1
CLK frequency at Data transfer Mode (PP)1
—10/30
cards
0
25/5
0
25/5
MHz
2
CLK frequency at Identification Mode2
0
400
0
400
KHz
3a
Clock high time1
—10/30 cards
6/33
10/50
ns
Table 28. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing Table (Continued)
Symbol
Description
Minimum
Corresponding Register Value
Unit
Bus Clock
5b
6b
6a
7
5a
4a
3a
CMD_DAT Input
CMD_DAT Output
4b
3b
Valid Data
1
2
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