參數(shù)資料
型號： MC8641DVU1250JC
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： MICROPROCESSOR, CBGA1023
封裝： 33 X 33 MM, ROHS COMPLIANT, CERAMIC, BGA-1023
文件頁數(shù)： 49/140頁
文件大?。?/td> 1484K
代理商： MC8641DVU1250JC
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 0
16
Freescale Semiconductor
Input Clocks
Table 7. SYSCLK DC Electrical Characteristics (OVDD = 3.3 V ± 165 mV.)
4.1
System Clock Timing
Table 8 provides the system clock (SYSCLK) AC timing specifications for the MPC8641.
4.1.1
SYSCLK and Spread Spectrum Sources
Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference emissions
(EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise magnitude in order to meet
industry and government requirements. These clock sources intentionally add long-term jitter in order to diffuse the
EMI spectral content. The jitter specification given in Table 8 considers short-term (cycle-to-cycle) jitter only and
the clock generator’s cycle-to-cycle output jitter should meet the MPC8641 input cycle-to-cycle jitter requirement.
Frequency modulation and spread are separate concerns, and the MPC8641 is compatible with spread spectrum
sources if the recommendations listed in Table 9 are observed.
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2OVDD + 0.3
V
Low-level input voltage
VIL
–0.3
0.8
V
Input current
(VIN
1 = 0 V or V
IN = VDD)
IIN
—±5
μA
Note:
1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
Table 8. SYSCLK AC Timing Specifications
At recommended operating conditions (see Table 2) with OVDD = 3.3 V ± 165 mV.
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
SYSCLK frequency
fSYSCLK
66
—
166.66
MHz
1
SYSCLK cycle time
tSYSCLK
6—
—
ns
—
SYSCLK rise and fall time
tKH, tKL
0.61.0
1.2ns
2
SYSCLK duty cycle
tKHK/tSYSCLK
40
—
60
%
3
SYSCLK jitter
—
150
ps
4, 5
Notes:
1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the
resulting SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective
maximum or minimum operating frequencies. Refer toSection 18.2, “MPX to SYSCLK PLL Ratio”, and
2. Rise and fall times for SYSCLK are measured at 0.4 V and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the short term jitter only and is guaranteed by design.
5. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to
allow cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter. Note that the
frequency modulation for SYSCLK reduces significantly for the spread spectrum source case. This is to guarantee
what is supported based on design.
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