參數(shù)資料
型號(hào)： MC8641DVU1250JC
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： MICROPROCESSOR, CBGA1023
封裝： 33 X 33 MM, ROHS COMPLIANT, CERAMIC, BGA-1023
文件頁數(shù)： 125/140頁
文件大小： 1484K
代理商： MC8641DVU1250JC
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
85
Serial RapidIO
For each baud rate at which an LP-Serial transmitter is specified to operate, the output eye pattern of the
transmitter shall fall entirely within the unshaded portion of the Transmitter Output Compliance Mask
shown in Figure 54 with the parameters specified in Table 58 when measured at the output pins of the
device and the device is driving a 100 Ohm +/–5% differential resistive load. The output eye pattern of an
LP-Serial transmitter that implements pre-emphasis (to equalize the link and reduce inter-symbol
interference) need only comply with the Transmitter Output Compliance Mask when pre-emphasis is
disabled or minimized.
Figure 54. Transmitter Output Compliance Mask
Table 57. Long Run Transmitter AC Timing Specifications—3.125 GBaud
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Output Voltage,
VO
-0.40
2.30
Volts
Voltage relative to COMMON
of either signal comprising a
differential pair
Differential Output Voltage
VDIFFPP
800
1600
mV p-p
Deterministic Jitter
JD
0.17
UI p-p
Total Jitter
JT
0.35
UI p-p
Multiple output skew
SMO
1000
ps
Skew at the transmitter output
between lanes of a multilane
link
Unit Interval
UI
320
ps
+/- 100 ppm
0
VDIFF min
VDIFF max
-VDIFF min
-VDIFF max
0B
1-B
1
Time in UI
T
ra
n
s
m
it
te
rDi
ff
e
rent
ia
l
Out
put
V
o
lt
age
A1-A
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