參數(shù)資料
型號: MC8640DTVU1000HE
廠商: Freescale Semiconductor
文件頁數(shù): 71/130頁
文件大?。?/td> 0K
描述: IC MPU DUAL CORE E600 1023FCCBGA
標準包裝: 1
系列: MPC86xx
處理器類型: 32-位 MPC86xx PowerPC
速度: 1.0GHz
電壓: 1.05V
安裝類型: 表面貼裝
封裝/外殼: 1023-BCBGA,F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝: 1023-FCCBGA(33x33)
包裝: 托盤
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
45
Local Bus
Figure 26 shows the local bus signals with PLL enabled.
Figure 26. Local Bus Signals (PLL Enabled)
NOTE
PLL bypass mode is recommended when LBIU frequency is at or below
83 MHz. When LBIU operates above 83 MHz, LBIU PLL is recommended
to be enabled.
Table 42 describes the general timing parameters of the local bus interface at OVDD = 3.3 V with PLL
bypassed.
Table 42. Local Bus Timing Parameters—PLL Bypassed
Parameter
Symbol1
Min
Max
Unit
Notes
Local bus cycle time
tLBK
12
ns
2
Local bus duty cycle
tLBKH/tLBK
45
55
%
Internal launch/capture clock to LCLK delay
tLBKHKT
2.3
3.9
ns
8
Input setup to local bus clock (except LGTA/LUPWAIT)
tLBIVKH1
5.7
ns
4, 5
LGTA/LUPWAIT input setup to local bus clock
tLBIVKL2
5.6
ns
4, 5
Input hold from local bus clock (except LGTA/LUPWAIT)
tLBIXKH1
–1.8
ns
4, 5
Output Signals:
LA[27:31]/LBCTL/LBCKE/LOE/
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
tLBKHOV1
tLBKHOV2
tLBKHOV3
LSYNC_IN
Input Signals:
LAD[0:31]/LDP[0:3]
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
Output (Address) Signal:
LAD[0:31]
LALE
tLBIXKH1
tLBIVKH1
tLBIVKH2
tLBIXKH2
tLBKHOX1
tLBKHOZ1
tLBKHOX2
tLBKHOZ2
Input Signal:
LGTA
tLBOTOT
tLBKHOZ2
tLBKHOX2
tLBKHOV4
LUPWAIT
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