參數(shù)資料
型號(hào): MC8640DTVU1000HE
廠商: Freescale Semiconductor
文件頁數(shù): 106/130頁
文件大?。?/td> 0K
描述: IC MPU DUAL CORE E600 1023FCCBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC86xx
處理器類型: 32-位 MPC86xx PowerPC
速度: 1.0GHz
電壓: 1.05V
安裝類型: 表面貼裝
封裝/外殼: 1023-BCBGA,F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝: 1023-FCCBGA(33x33)
包裝: 托盤
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
77
Serial RapidIO
5. The peak value of the differential transmitter output signal and the differential receiver input
signal is A – B volts
6. The peak-to-peak value of the differential transmitter output signal and the differential receiver
input signal is 2
× (A – B) volts
Figure 53. Differential Peak-Peak Voltage of Transmitter or Receiver
To illustrate these definitions using real values, consider the case of a current mode logic (CML)
transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing
that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of the signals TD
and TD is 500 mV p-p. The differential output signal ranges between 500 mV and –500 mV. The peak
differential voltage is 500 mV. The peak-to-peak differential voltage is 1000 mV p-p.
15.4
Equalization
With the use of high speed serial links, the interconnect media causes degradation of the signal at the
receiver. Effects such as inter-symbol interference (ISI) or data-dependent jitter are produced. This loss
can be large enough to degrade the eye opening at the receiver beyond what is allowed in the specification.
To negate a portion of these effects, equalization can be used. The most common equalization techniques
that can be used are:
A passive high pass filter network placed at the receiver, often referred to as passive equalization.
The use of active circuits in the receiver, often referred to as adaptive equalization.
15.5
Explanatory Note on Transmitter and Receiver Specifications
AC electrical specifications are given for transmitter and receiver. Long run and short run interfaces at
three baud rates (a total of six cases) are described.
The parameters for the AC electrical specifications are guided by the XAUI electrical interface specified
in clause 47 of IEEE 802.3ae-2002.
XAUI has similar application goals to the serial RapidIO interface. The goal of this standard is that
electrical designs for the serial RapidIO interface can reuse electrical designs for XAUI, suitably modified
for applications at the baud intervals and reaches described herein.
Differential Peak-Peak = 2 * (A-B)
A Volts
TD or RD
B Volts
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