參數(shù)資料
型號： MC8640DTVU1000HE
廠商： Freescale Semiconductor
文件頁數(shù)： 45/130頁
文件大?。?/td> 0K
描述： IC MPU DUAL CORE E600 1023FCCBGA
標(biāo)準(zhǔn)包裝： 1
系列： MPC86xx
處理器類型： 32-位 MPC86xx PowerPC
速度： 1.0GHz
電壓： 1.05V
安裝類型： 表面貼裝
封裝/外殼： 1023-BCBGA，F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝： 1023-FCCBGA（33x33）
包裝： 托盤
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
21
DDR and DDR2 SDRAM
6.2
DDR SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM interface.
6.2.1
DDR SDRAM Input AC Timing Specifications
Table 18 provides the input AC timing specifications for the DDR2 SDRAM when Dn_GVDD(typ) =1.8 V.
Table 19 provides the input AC timing specifications for the DDR SDRAM when Dn_GVDD(typ) =2.5 V.
Table 20 provides the input AC timing specifications for the DDR SDRAM interface.
Table 18. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
At recommended operating conditions (see Table 2)
Parameter
Symbol
Min
Max
Unit
Notes
AC input low voltage
VIL
—D
n_MVREF – 0.25
V
—
AC input high voltage
VIH
D
n_MVREF + 0.25
—
V
—
Table 19. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface
At recommended operating conditions (see Table 2)
Parameter
Symbol
Min
Max
Unit
Notes
AC input low voltage
VIL
—D
n_MVREF – 0.31
V
—
AC input high voltage
VIH
D
n_MVREF + 0.31
—
V
—
Table 20. DDR SDRAM Input AC Timing Specifications
At recommended operating conditions (see Table 2)
Parameter
Symbol
Min
Max
Unit
Notes
Controller Skew for
MDQS—MDQ/MECC
tCISKEW
—
ps
1, 2
533 MHz
—
–300
300
—
3
400 MHz
—
–365
365
—
Note:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
will be captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be
determined by the following equation: tDISKEW = ±(T 4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the
absolute value of tCISKEW.
3. Maximum DDR1 frequency is 400 MHz.
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