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參數(shù)資料
型號： MC8640DHX1250HE
廠商： Freescale Semiconductor
文件頁數(shù)： 82/130頁
文件大小： 0K
描述： IC DUAL CORE PROCESSOR 1023-CBGA
標準包裝： 1
系列： MPC86xx
處理器類型： 32-位 MPC86xx PowerPC
速度： 1.25GHz
電壓： 1.05V
安裝類型： 表面貼裝
封裝/外殼： 1023-BCBGA，F(xiàn)CCBGA
供應商設備封裝： 1023-FCCBGA（33x33）
包裝： 托盤
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
55
I
2C
12.2
I2C AC Electrical Specifications
Table 46 provides the AC timing parameters for the I2C interfaces.
Input current each I/O pin (input voltage is between
0.1
× OVDD and 0.9 × OVDD (max)
II
–10
10
μA3
Capacitance for each I/O pin
CI
—10
pF
—
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. Refer to the
MPC8641 Integrated Host Processor Reference Manual for information on the digital filter used.
3. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off.
Table 46. I2C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 45).
Parameter
Symbol1
Min
Max
Unit
SCL clock frequency
fI2C
0
400
kHz
Low period of the SCL clock
tI2CL
4
1.3
—
μs
High period of the SCL clock
tI2CH
4
0.6
—
μs
Setup time for a repeated START condition
tI2SVKH
4
0.6
—
μs
Hold time (repeated) START condition (after this period, the first
clock pulse is generated)
tI2SXKL
4
0.6
—
μs
Data setup time
tI2DVKH
4
100
—
ns
Data input hold time:
CBUS compatible masters
I2C bus devices
tI2DXKL
—
0 2
—
μs
Rise time of both SDA and SCL signals
tI2CR
20 + 0.1 CB
5
300
ns
Fall time of both SDA and SCL signals
tI2CF
20 + 0.1 Cb
5
300
ns
Data output delay time
tI2OVKL
—0.9 3
μs
Set-up time for STOP condition
tI2PVKH
0.6
—
μs
Bus free time between a STOP and START condition
tI2KHDX
1.3
—
μs
Noise margin at the LOW level for each connected device (including
hysteresis)
VNL
0.1
× OVDD
—V
Table 45. I2C DC Electrical Characteristics (continued)
At recommended operating conditions with OVDD of 3.3 V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
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