參數(shù)資料
型號： MC8640DHX1250HE
廠商： Freescale Semiconductor
文件頁數(shù)： 41/130頁
文件大?。?/td> 0K
描述： IC DUAL CORE PROCESSOR 1023-CBGA
標準包裝： 1
系列： MPC86xx
處理器類型： 32-位 MPC86xx PowerPC
速度： 1.25GHz
電壓： 1.05V
安裝類型： 表面貼裝
封裝/外殼： 1023-BCBGA，F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝： 1023-FCCBGA（33x33）
包裝： 托盤
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
18
Freescale Semiconductor
RESET Initialization
Note that at MPX = 400 MHz, cfg_plat_freq = 0 and at MPX > 400 MHz, cfg_plat_freq = 1. Therefore,
when operating PCI Express in x8 link width, the MPX platform frequency must be 400 MHz with
cfg_plat_freq = 0 or greater than or equal to 527 MHz with cfg_plat_freq = 1.
For proper Serial RapidIO operation, the MPX clock frequency must be greater than:
2 × (0.80) × (Serial RapidIO interface frequency) × (Serial RapidIO link width)
64
4.5
Other Input Clocks
For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC,
see the specific section of this document.
5
RESET Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements of
the MPC8640. Table 11 provides the RESET initialization AC timing specifications.
Table 12 provides the PLL lock times.
Table 11. RESET Initialization Timing Specifications
Parameter
Min
Max
Unit
Notes
Required assertion time of HRESET
100
—
μs—
Minimum assertion time for SRESET_0 & SRESET_1
3
—
SYSCLKs
1
Platform PLL input setup time with stable SYSCLK before HRESET
negation
100
—
μs2
Input setup time for POR configs (other than PLL config) with respect to
negation of HRESET
4
—
SYSCLKs
1
Input hold time for all POR configs (including PLL config) with respect to
negation of HRESET
2
—
SYSCLKs
1
Maximum valid-to-high impedance time for actively driven POR configs
with respect to negation of HRESET
—
5
SYSCLKs
1
Notes:
1. SYSCLK is the primary clock input for the MPC8640.
2 This is related to HRESET assertion time. Stable PLL configuration inputs are required when a stable SYSCLK is applied. See
the
MPC8641D Integrated Host Processor Reference Manual for more details on the power-on reset sequence.
Table 12. PLL Lock Times
Parameter
Min
Max
Unit
Notes
(Platform and E600) PLL lock times
—
100
μs1
Local bus PLL
—
50
μs—
Notes:
1.The PLL lock time for e600 PLLs require an additional 255 MPX_CLK cycles.
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MC8640DHX1250N 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications Addendum for the MC8640xTxxyyyyaC Series
MC8640DTHX1000H 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications
MC8640DTHX1000HC 功能描述:微處理器 - MPU G8 REV2.1 1.05V -40/105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324
MC8640DTHX1000HE 功能描述:微處理器 - MPU G8 REV 3.0 1.05V -40/105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324
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