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參數(shù)資料
| 型號： | MC68LC302PU20VCT |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100 |
| 文件頁數(shù)： | 43/128頁 |
| 文件大?。?/td> | 641K |
| 代理商： | MC68LC302PU20VCT |
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MC68EN302 Module Bus Controller
2-4
MC68EN302 REFERENCE MANUAL
MOTOROLA
302 GIMR. For proper operation of the MC68EN302, the MOD bit must be zero in the
internal 302 core.
0 = Configures the pins as IPL2-IPL0.
1 = Configures the pins as IRQ7, IRQ6, and IRQ1.
Bits 14–12—Reserved. Should be written as zero. These bits are always read as zero.
MIL—Module Interrupt Level. This bit determines the interrupt level at which Module Bus
Controller interrupts are generated. Because the interrupt level of the internal 302 core is set
at 4, and this bit predetermines the Module Bus Controller interrupt at either level 3 or 5,
external interrupts should not be generated at level 4 or the level preset by MIL.
0 = Interrupts are generated at level 5
1 = Interrupts are generated at level 3.
IET7—Interrupt Edge Trigger Level 7. This bit has no effect unless IMOD=1 and replaces
the operation of the ET7 bit in the Global Interrupt Mode Register (GIMR) of the internal 302
core. The ET7 bit in the GIMR register must equal zero for correct interrupt operation
0 = An interrupt is made pending when IRQ7 is low.
1 = An interrupt is made pending when IRQ7 changes from a one to a zero (falling
edge) of the MC68EN302.
IET6—Interrupt Edge Trigger Level 6. This bit is has no affect unless IMOD is one. This bit
replaces the functionality of the ET6 bit in the Global Interrupt Mode Register (GIMR) of the
internal 302 core. The ET6 bit in the GIMR register must be set to zero.
0 = An interrupt is made pending when IRQ6 is low.
1 = An interrupt is made pending when IRQ6 changes from a one to a zero (falling
edge).
IET1—Interrupt Edge Trigger Level 1. This bit is has no effect unless IMOD is one. This bit
replaces the functionality of the ET1 bit in the Global Interrupt Mode Register (GIMR) of the
internal 302 core. The ET1 bit in the GIMR register must be set to zero.
0 = An interrupt is made pending when IRQ1 is low.
1 = An interrupt is made pending when IRQ1 changes from a one to a zero (falling
edge).
Bits 7–0—Reserved. Should be written as zero. These bits are always read as zero.
2.6 CHIP SELECT EXTENSION REGISTERS (CSER3–CSER0)
These registers provide additional functionality above the 68302 chip selects including 8-bit
bus operation and parity generation and checking. Before setting the FCE, DT2–DT0 or EN8
bits, be sure that an external DTACK is supported by programming the 302 DTACK field in
the corresponding OR register to 111. These registers are initialized to 0x000C or 0x000D
upon hard reset (refer to the EN8 bit for more detail).
If at RESET, the 8-bit mode is selected through use of the PARITY1/BUSW pin, the DTACK
field in OR0 of the 302 core is forced to 111. This results in the DT2–DT0 field of CSER0
controlling DTACK.
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