參數(shù)資料
型號： MC68LC302PU20VCT
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100
文件頁數(shù)： 22/128頁
文件大?。?/td> 641K
代理商： MC68LC302PU20VCT
MC68302 Product Summary Page
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Line Cards
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Network Bridges
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Gateways
Technical Specifications
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MC68000/MC68008 Microprocessor Core (May be disabled to use the IMP as a peripheral)
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SIB Including:
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Independent Direct Memory Access (IDMA) Controller
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Interrupt controller with two modes of operation
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Parallel I/O ports, some with interrupt capability
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On-Chip 1152-bytes of dual-port RAM
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Three timers, with a software watchdog timer
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Four programmable chip-select lines with wait-state logic
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Programmable address mapping of dual-port RAM and IMP registers
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On-Chip clock generator with an output clock signal
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System Control
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Bus arbitration logic with low interrupt latency support
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System control register
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Hardware watchdog for monitoring bus activity
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Low power (Standby) modes
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Disable CPU logic (M68000)
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Freeze control for debugging selected on-chip peripherals
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DRAM refresh controller
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CP Including:
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Main controller (RISC Processor)
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Three full-duplex Serial Communication/Controllers with the following protocols:
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HDLC/SDLC
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Bisync
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UART
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DDCMP
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Totally Transparent
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V.110
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Six serial DMA channels dedicated to the three SOCs
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Capability to send/receive up to eight buffers/frames without M68000 core intervention
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Flexible physical interface accessible by SCCs for Inter-chip Digital Link (IDL), General Circuit Interface
(GCI).
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Pulse Code Modulation (PCM), and Non-multiplexed Serial Interface (NMSI) Operation.
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Serial Communication Port (SCP) for synchronous communication.
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Two Serial Management Controllers (SMCs) for IDL and GCI Channel.
MC68302 Parametrics
Description
Processor Speed
(MHz)
Bus Interface
(Bits)
Memory
Voltage
(V)
Package
Performance
file:///H|/imaging/BITTING/CPL/20021108_2/11072002_10/MOTO/11072002_HTML/MC68302.htm (2 of 12) [11/12/02 2:08:15 PM]
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