參數(shù)資料
型號： MC68LC302PU20VCT
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100
文件頁數(shù)： 107/128頁
文件大?。?/td> 641K
代理商： MC68LC302PU20VCT
Table of Contents
Paragraph
Title
Page
Number
MOTOROLA
MC68EN302 USER’S MANUAL
ix
5.3.1
RMC/IOUT1............................................................................................. 5-5
5.3.2
IAC .......................................................................................................... 5-6
5.3.3
BCLR....................................................................................................... 5-6
5.3.4
FRZ ......................................................................................................... 5-6
5.3.5
BUSW...................................................................................................... 5-6
5.3.6
DISCPU................................................................................................... 5-6
5.4
MC68EN302 New Signals Muxed with Existing MC68302 Signals......... 5-6
5.4.1
AMUX - DRAM Address Mux .................................................................. 5-7
5.4.2
RAS0 - DRAM Row Address Select, Bit Zero ......................................... 5-7
5.4.3
RAS1 - DRAM Row Address Select Bit 1................................................ 5-7
5.4.4
CAS0 - DRAM Column Address Select Bit 0 .......................................... 5-7
5.4.5
CAS1- DRAM Column Address Select Bit 1 ........................................... 5-7
5.4.6
DRAMRW- DRAM Read/Write ................................................................ 5-7
5.4.7
A0 ............................................................................................................ 5-8
5.4.8
WEL- Write Enable for Byte 1 (Bit 7–Bit 0).............................................. 5-8
5.4.9
WEH - Write Enable for Byte 0 (Bit 15–Bit 8) .......................................... 5-8
5.4.10
OE - Output Enable ................................................................................. 5-8
5.5
MC68EN302 Only Pin/Signals ................................................................ 5-8
5.5.1
GND ........................................................................................................ 5-8
5.5.2
TRST - JTAG Reset Signal ..................................................................... 5-8
5.5.3
TMS - JTAG Test Mode Select ............................................................... 5-9
5.5.4
TDO - JTAG Test Data Out ..................................................................... 5-9
5.5.5
TDI - JTAG Test Data In.......................................................................... 5-9
5.5.6
TCK- JTAG Clock.................................................................................... 5-9
5.5.7
GND ........................................................................................................ 5-9
5.5.8
TENA....................................................................................................... 5-9
5.5.9
TCLK ....................................................................................................... 5-9
5.5.10
RCLK....................................................................................................... 5-9
5.5.11
RX ........................................................................................................... 5-9
5.5.12
RENA ...................................................................................................... 5-9
5.5.13
CLSN....................................................................................................... 5-9
5.5.14
PARITY0/DISCPU................................................................................... 5-9
5.5.15
PARITY1/BUSW.................................................................................... 5-10
5.5.16
PARITYE/THREESTATE ...................................................................... 5-10
5.6
DRAM Controller I/O ............................................................................. 5-10
5.6.1
Control Signal Pins................................................................................ 5-10
5.6.2
Column Address Strobes (CAS1–CAS0) .............................................. 5-10
5.6.3
Row Address Strobes (RAS1–RAS0) ................................................... 5-10
5.6.4
DRAM Read/Write (DRAMRW)............................................................. 5-10
5.6.5
Address Mux (AMUX)............................................................................ 5-11
5.6.6
Parity (PARITY1–PARITY0).................................................................. 5-11
5.6.7
Muxing Scheme..................................................................................... 5-11
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