
20-2
MPC561/MPC563 Reference Manual
MOTOROLA
Features
20.1 Features
Eight Kbytes of static RAM
Accessible by the CPU only if neither TPU3 is in emulation mode
Low-power stop operation
— Entered by setting the STOP bit in the DPTMCR
— Does not enter low-power state while in TPU3 emulation mode for protection
TPU3 microcode mode
— The DPTRAM array acts as a microcode storage for the TPU3 module. This
provides a means of executing TPU3 code out of DPTRAM instead of TPU3
ROM.
Includes built in check logic which scans the array contents and calculates the
DPTRAM signature
IMB3 bus interface
Two TPU3 interface units
Byte, half-word, or word accessible
20.2 DPTRAM Configuration Block Diagram
Figure 20-1. DPTRAM Configuration
IM
B3
TPU3 Emulation Mode
TPU3
Local Bus
RAM Mode
DPTRAM
TPU3
DPTRAM
IM
B
3
IM
B3
IM
B
3