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參數(shù)資料
| 型號： | MC68HLC705KJ1CP |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 75/117頁 |
| 文件大?。?/td> | 1644K |
| 代理商： | MC68HLC705KJ1CP |
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Low-Power Modes
Data Sheet
MC68HC705KJ1MC68HRC705KJ1MC68HLC705KJ1 — Rev. 4.0
60
Low-Power Modes
MOTOROLA
Exiting Wait Mode
External reset — A logic 0 on the RESET pin resets the MCU, starts the CPU
clock, and loads the program counter with the contents of locations $07FE
and $07FF.
External interrupt — A high-to-low transition on the IRQ/VPP pin or a
low-to-high transition on an enabled port A external interrupt pin starts the
CPU clock and loads the program counter with the contents of locations
$07FA and $07FB.
COP watchdog reset — A timeout of the COP watchdog resets the MCU,
starts the CPU clock, and loads the program counter with the contents of
locations $07FE and $07FF. Software can enable timer interrupts so that the
MCU periodically can exit wait mode to reset the COP watchdog.
Timer interrupt — Real-time interrupt requests and timer overflow interrupt
requests start the MCU clock and load the program counter with the
contents of locations $07F8 and $07F9.
6.3 Effects of Stop and Wait Modes
The STOP and WAIT instructions have the following effects on MCU modules.
6.3.1 Clock Generation
Effects of STOP and WAIT on clock generation are discussed here.
6.3.1.1 STOP
The STOP instruction disables the internal oscillator, stopping the CPU clock and
all peripheral clocks.
After exiting stop mode, the CPU clock and all enabled peripheral clocks begin
running after the oscillator stabilization delay.
NOTE:
The oscillator stabilization delay holds the MCU in reset for the first 4064 internal
clock cycles.
6.3.1.2 WAIT
The WAIT instruction disables the CPU clock.
After exiting wait mode, the CPU clock and all enabled peripheral clocks
immediately begin running.
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