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參數(shù)資料
| 型號(hào)： | MC68HLC705KJ1CP |
| 廠(chǎng)商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁(yè)數(shù)： | 56/117頁(yè) |
| 文件大?。?/td> | 1644K |
| 代理商： | MC68HLC705KJ1CP |
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Central Processor Unit (CPU)
Instruction Set
MC68HC705KJ1MC68HRC705KJ1MC68HLC705KJ1 — Rev. 4.0
Data Sheet
MOTOROLA
Central Processor Unit (CPU)
43
4.6.2.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its contents, and
write the modified value back to the memory location or to the register.
NOTE:
Do not use read-modify-write instructions on registers with write-only bits.
4.6.2.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the program
counter. The unconditional jump instruction (JMP) and the jump-to-subroutine
instruction (JSR) have no register operand. Branch instructions allow the CPU to
interrupt the normal sequence of the program counter when a test condition is met.
If the test condition is not met, the branch is not performed.
The BRCLR and BRSET instructions cause a branch based on the state of any
readable bit in the first 256 memory locations. These 3-byte instructions use a
combination of direct addressing and relative addressing. The direct address of the
byte to be tested is in the byte following the opcode. The third byte is the signed
offset byte. The CPU finds the effective branch destination by adding the third byte
to the program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is from –128
Table 4-2. Read-Modify-Write Instructions
Instruction
Mnemonic
Arithmetic Shift Left (Same as LSL)
ASL
Arithmetic Shift Right
ASR
Bit Clear
BCLR(1)
1. Unlike other read-modify-write instructions, BCLR and
BSET use only direct addressing.
Bit Set
BSET(1)
Clear Register
CLR
Complement (One’s Complement)
COM
Decrement
DEC
Increment
INC
Logical Shift Left (Same as ASL)
LSL
Logical Shift Right
LSR
Negate (Two’s Complement)
NEG
Rotate Left through Carry Bit
ROL
Rotate Right through Carry Bit
ROR
Test for Negative or Zero
TST(2)
2. TST is an exception to the read-modify-write sequence
because it does not write a replacement value.
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