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參數(shù)資料
| 型號(hào)： | MC68HLC705KJ1CP |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 29/117頁 |
| 文件大?。?/td> | 1644K |
| 代理商： | MC68HLC705KJ1CP |
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Introduction
Pin Functions
MC68HC705KJ1MC68HRC705KJ1MC68HLC705KJ1 — Rev. 4.0
Data Sheet
MOTOROLA
Introduction
19
1.4.2.3 RC Oscillator
Refer to Appendix A. MC68HRC705KJ1.
1.4.2.4 External Clock
An external clock from another CMOS-compatible device can be connected to the
OSC1 input, with the OSC2 input not connected, as shown in Figure 1-8. This
configuration is possible regardless of whether the crystal/ceramic resonator or the
RC oscillator is enabled.
Figure 1-8. External Clock Connections
1.4.3 RESET
Applying a logic 0 to the RESET pin forces the MCU to a known startup state. An
internal reset also pulls the RESET pin low. An internal resistor to VDD pulls the
RESET pin high. A steering diode between the RESET and VDD pins discharges
any RESET pin voltage when power is removed from the MCU. The RESET pin
contains an internal Schmitt trigger to improve its noise immunity as an input. Refer
to Section 8. Resets and Interrupts for more information.
1.4.4 IRQ/VPP
The external interrupt/programming voltage pin (IRQ/VPP) drives the
asynchronous IRQ interrupt function of the CPU. Additionally, it is used to program
the user EPROM and mask option register. (See Section 2. Memory and Section
The LEVEL bit in the mask option register provides negative edge-sensitive
triggering or both negative edge-sensitive and low level-sensitive triggering for the
interrupt function.
If level-sensitive triggering is selected, the IRQ/VPP input requires an external
resistor to VDD for wired-OR operation. If the IRQ/VPP pin is not used, it must be
tied to the VDD supply.
MCU
EXTERNAL
CMOS CLOCK
OSC1
OSC2
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