參數(shù)資料
型號： MC68HCL05C9AFN
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 143/162頁
文件大?。?/td> 1093K
代理商： MC68HCL05C9AFN
Serial Communications Interface (SCI)
Start Bit Detection
MC68HC05C9A — Rev. 5.0
Advance Information
MOTOROLA
Serial Communications Interface (SCI)
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9.10 Start Bit Detection
When the input (idle) line is detected low, it is tested for three more
sample times (referred to as the start edge verification samples in
Figure 9-4). If at least two of these three verification samples detect a
logic 0, a valid start bit has been detected; otherwise, the line is assumed
to be idle. A noise flag is set if all three verification samples do not detect
a logic 0. Thus, a valid start bit could be assumed with a set noise flag
present.
If a framing error has occurred without detection of a break (10 0s for 8-
bit format or 11 0s for 9-bit format), the circuit continues to operate as if
there actually was a stop bit, and the start edge will be placed artificially.
The last bit received in the data shift register is inverted to a logic 1, and
the three logic 1 start qualifiers (shown in Figure 9-4) are forced into the
sample shift register during the interval when detection of a start bit is
anticipated (see Figure 9-6); therefore, the start bit will be accepted no
sooner than it is anticipated.
Figure 9-6. SCI Artificial Start Following a Frame Error
DATA
EXPECTED STOP
DATA SAMPLES
ARTIFICIAL EDGE
START BIT
DATA
RDI
DATA
EXPECTED STOP
DATA SAMPLES
START EDGE
START BIT
DATA
RDI
a) Case 1: Receive Line Low During Artificial Edge
b) Case 2: Receive Line High During Expected Start Edge
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