參數(shù)資料
型號： MC68HCL05C9AFN
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 140/162頁
文件大小： 1093K
代理商： MC68HCL05C9AFN
Serial Communications Interface (SCI)
Receiver Wakeup Operation
MC68HC05C9A — Rev. 5.0
Advance Information
MOTOROLA
Serial Communications Interface (SCI)
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The receiver is placed in wakeup mode by setting the receiver wakeup
bit (RWU) in the SCCR2 register. While RWU is set, all of the receiver-
related status flags (RDRF, IDLE, OR, NF, and FE) are inhibited (cannot
become set).
NOTE:
The idle line detect function is inhibited while the RWU bit is set.
Although RWU may be cleared by a software write to SCCR2, it would
be unusual to do so.
Normally, RWU is set by software and is cleared automatically in
hardware by one of these methods: idle line wakeup or address mark
wakeup.
9.8.1 Idle Line Wakeup
In idle line wakeup mode, a dormant receiver wakes up as soon as the
RDI line becomes idle. Idle is defined as a continuous logic high level on
the RDI line for 10 (or 11) full bit times. Systems using this type of
wakeup must provide at least one character time of idle between
messages to wake up sleeping receivers, but must not allow any idle
time between characters within a message.
9.8.2 Address Mark Wakeup
In address mark wakeup, the most significant bit (MSB) in a character is
used to indicate whether it is an address (logic 1) or data (logic 0)
character. Sleeping receivers will wake up whenever an address
character is received. Systems using this method for wakeup would set
the MSB of the first character of each message and leave it clear for all
other characters in the message. Idle periods may be present within
messages and no idle time is required between messages for this
wakeup method.
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