參數(shù)資料
型號： MC68HC916X1
廠商： Motorola, Inc.
英文描述： 16-Bit Modular Microcontroller(16位模塊化微控制器)
中文描述： 16位微控制器模塊（16位模塊化微控制器）
文件頁數(shù)： 24/172頁
文件大?。?/td> 1035K
代理商： MC68HC916X1
MOTOROLA
24
MC68HC916X1
MC68HC916X1TS/D
W — Frequency Control Bit
This bit controls a prescaler tap in the synthesizer feedback loop. Setting the bit increases the VCO
speed by a factor of four. VCO relock delay is required.
X — Frequency Control Bit
This bit controls a divide by two prescaler that is not in the synthesizer feedback loop. Setting it doubles
clock speed without changing VCO speed. There is no VCO relock delay.
Y[5:0] — Frequency Control
The Y field controls the modulus down counter in the synthesizer feedback loop, which effectively allows
frequency multiplication by a value of Y + 1. VCO relock delay is required.
EDIV — ECLK Divide Rate
0 = ECLK frequency is system clock divided by 8
1 = ECLK frequency is system clock divided by 16
ECLK is an external M6800 bus clock available on pin ADDR23. Refer to
3.9 Chip Selects
for more
information.
SLOCK — Synthesizer Lock Flag
0 = VCO is enabled, but has not locked
1 = VCO has locked on the desired frequency (or system clock is external)
The MCU remains in reset until the synthesizer locks, but SLOCK does not indicate synthesizer lock
status until after the user writes to SYNCR.
STSCIM — Stop Mode SCIM Clock
0 = When LPSTOP is executed, the SCIM clock is driven from the crystal oscillator and the VCO is
turned off to conserve power.
1 = When LPSTOP is executed, the SCIM clock is driven from the VCO.
STEXT — Stop Mode External Clock
0 = When LPSTOP is executed, the CLKOUT signal is held negated to conserve power.
1 = When LPSTOP is executed, the CLKOUT signal is driven from the SCIM clock, as determined
by the state of the STSCIM bit.
3.3.4 Periodic Interrupt Timer
The periodic interrupt timer (PIT) generates interrupts of specified priorities at specified intervals.
Timing for the PIT is provided by a programmable prescaler driven by the system clock.
This register contains information concerning periodic interrupt priority and vectoring. Bits [10:0]
can be read or written at any time. Bits [15:11] are unimplemented and always return zero.
PIRQL[2:0] — Periodic Interrupt Request Level
Table 14
shows what interrupt request level is asserted when a periodic interrupt is generated. If a PIT
interrupt and an external interrupt request of the same priority occur simultaneously, the PIT interrupt
is serviced first. The periodic timer continues to run when the interrupt is disabled.
PICR
— Periodic Interrupt Control Register
$YFFA22
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
PIRQL[2:0]
PIV[7:0]
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
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