參數資料
型號： MC68HC916X1
廠商： Motorola, Inc.
英文描述： 16-Bit Modular Microcontroller(16位模塊化微控制器)
中文描述： 16位微控制器模塊（16位模塊化微控制器）
文件頁數： 145/172頁
文件大?。?/td> 1035K
代理商： MC68HC916X1
MC68HC916X1
MC68HC916X1TS/D
MOTOROLA
145
Table 78 AC Timing
(V
DD
and V
DDSYN
= 5.0 Vdc
±
10%, V
SS
= 0 Vdc, T
A
= T
L
to T
H
)
1
Num
F1
1
1A
1B
2, 3
2A, 3A ECLK Pulse Width
2B, 3BExternal Clock Input High/Low Time
3
4, 5
CLKOUT Rise and Fall Time
4A, 5A Rise and Fall Time (All Outputs except CLKOUT)
4B, 5B External Clock Input Rise and Fall Time
4
6
Clock High to ADDR, FC, SIZE Valid
7
Clock High to ADDR, Data, FC, SIZE, High Impedance
8
Clock High to ADDR, FC, SIZE, Invalid
9
Clock Low to AS, DS, CS Asserted
9A
AS to DS or CS Asserted (Read)
5
11
ADDR, FC, SIZE Valid to AS, CS, (and DS Read) Asserted
12
Clock Low to AS, DS, CS Negated
13
AS, DS, CS Negated to ADDR, FC SIZE Invalid (Address Hold)
14
AS, CS (and DS Read) Width Asserted
14A
DS, CS Width Asserted (Write)
14B
AS, CS (and DS Read) Width Asserted (Fast Cycle)
15
AS, DS, CS Width Negated
6
16
Clock High to AS, DS, R/W High Impedance
17
AS, DS, CS Negated to R/W High
18
Clock High to R/W High
20
Clock High to R/W Low
21
R/W High to AS, CS Asserted
22
R/W Low to DS, CS Asserted (Write)
23
Clock High to Data Out Valid
24
Data Out Valid to Negating Edge of AS, CS (Fast Write Cycle)
25
DS, CS Negated to Data Out Invalid (Data Out Hold)
26
Data Out Valid to DS, CS Asserted (Write)
27
Data In Valid to Clock Low (Data Setup)
27A
Late BERR Asserted to Clock Low (Setup Time)
28
AS, DS Negated to DSACK1, BERR, Negated
29
DS, CS Negated to Data In Invalid (Data In Hold)
7
29A
DS, CS Negated to Data In High Impedance
7,
8
30
CLKOUT Low to Data In Invalid (Fast Cycle Hold)
7
30A
CLKOUT Low to Data In High Impedance
7
Characteristic
Symbol
f
t
cyc
t
Ecyc
t
Xcyc
t
CW
t
ECW
t
XCHL
t
Crf
t
rf
t
XCrf
t
CHAV
t
CHAZx
t
CHAZn
t
CLSA
t
STSA
t
AVSA
t
CLSN
t
SNAI
t
SWA
t
SWAW
t
SWDW
t
SN
t
CHSZ
t
SNRN
t
CHRH
t
CHRL
t
RAAA
t
RASA
t
CHDO
t
DVASN
t
SNDOI
t
DVSA
t
DICL
t
BELCL
t
SNDN
t
SNDI
t
SHDI
Min
Max
16.78
—
—
—
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
Frequency of Operation
2
Clock Period
ECLK Period
External Clock Input Period
3
Clock Pulse Width
4 f(ref)/128
59.6
476
59.6
28
236
29.8
—
—
—
0
0
0
2
-15
15
2
15
100
45
40
40
—
15
0
0
15
70
—
15
15
15
5
20
0
0
5
8
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
29
59
—
25
15
—
29
—
—
—
—
—
59
—
29
29
—
—
29
—
—
—
—
—
80
—
55
—
t
CLDI
15
—
ns
t
CLDH
—
90
ns
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